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Semiconductor Manufacturing, IEEE Transactions on

Issue 2 • Date May 2004

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  • Table of contents

    Page(s): c1 - c4
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Page(s): c2
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  • Junction-isolated electrical test structures for critical dimension calibration standards

    Page(s): 79 - 83
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB) |  | HTML iconHTML  

    The National Institute of Standards and Technology (NIST) is developing single-crystal reference materials for use as critical dimension (CD) reference materials. In earlier work, the reference features on these reference materials have been patterned in the device layer of a silicon-on-insulator (SOI) wafers, with the buried oxide providing electrical isolation. This paper describes a new method of isolating the structures from the substrate by means of a pn junction. The junction isolation technique is expected to provide several advantages over the SOI technique including minimal susceptibility to charging when imaged in a CD scanning electron microscope (CDSEM), better edge quality, and ease of manufacture. Primary calibration of these reference materials is by imaging the cross-section of the feature with high-resolution transmission electron microscopy (HRTEM) at sufficiently high energy to resolve and count the individual lattice planes while electrical test structure metrology techniques provide the transfer calibration. Secondary calibration is performed with electrical test structure metrology, supplemented by visual techniques to verify that the features meet uniformity requirements. In this paper, we describe results for determining the electrical critical dimensions of these junction-isolated structures. This measurement and data analysis technique is a unique combination of the short-bridge variation of the cross-bridge resistor and the multi-bridge structure. View full abstract»

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  • Design rules to minimize the effect of joule heating in Greek cross test structures

    Page(s): 84 - 90
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    This paper presents work on the analysis of the effect of Joule heating on sheet resistivity measurements using Greek cross test structures. As part of this work, design rules have been derived to minimize the heating effect associated with currents forced during their measurement. To accomplish this, finite-element (FE) simulations were employed to identify the location of heat generation and cooling mechanisms in the structures. This identified that the temperature could be minimized by: firstly, decreasing cross arm length, and therefore both electrical and thermal resistance of the arms; and secondly, by integrating pads and leads to improve the heat sink effect. These results were confirmed by sheet resistance measurements of four different Greek cross designs which demonstrated that the proposed design rules reduced the Joule heating effects on the sheet resistance measurements by up to 25%. View full abstract»

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  • Characterization of platinum films produced by UV exposure of a novel photosensitive organometallic material

    Page(s): 91 - 97
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    A novel process is presented which produces platinum features using direct UV exposure of the photosensitive organometallic material. The technique reduces the number of process steps involved when creating a metal pattern on a substrate by not requiring photoresist, solvents, or etch processes. In contrast to processes already reported in the literature, the method is compatible with microelectronic processes and does not require costly special equipment. Two test chips with MOS capacitors and resistive structures fabricated using the new organometallic material have been characterized. The results show that the deposited films are metallic and have a good adhesion to silicon dioxide. The work function of the platinum films is in agreement with the value found in the literature, but the measured resistivity and XPS indicate that the metal film contains some remaining organometallic residue after pattern development. View full abstract»

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  • A nondestructive electrical test structure to monitor deep trench depth for automated parametric process control

    Page(s): 98 - 103
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB) |  | HTML iconHTML  

    A novel nondestructive measurement technique is proposed to electrically monitor the depth of a trench etched in silicon for the purpose of process control in a manufacturing environment. A simple bipolar npn transistor can be constructed, the gain of which is shown to relate to the trench depth. The ratio of the injected emitter current to the captured collector current has demonstrated the ability to resolve variations in trench depth of less than 0.2 μm. The proposed structure is studied using two-dimensional simulations and experiments. A case study of two different silicon reactive ion etch tools is offered to demonstrate the effectiveness of the proposed technique. View full abstract»

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  • An advanced defect-monitoring test structure for electrical screening and defect localization

    Page(s): 104 - 110
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (760 KB) |  | HTML iconHTML  

    A new test structure for the detection and localization of short and open defects in large-scale integrated intralayer wiring processes is proposed. In the structure, an open-monitoring element in the first metal layer meanders around lines of short-monitoring elements placed in contact with N-type diffusion regions to make the structure compact. The proposed structure allows defective test structures to be screened through electrical measurements and killer defects to be localized through voltage contrast or optical microscopy methods. View full abstract»

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  • Development of a large-scale TEG for evaluation and analysis of yield and variation

    Page(s): 111 - 122
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3424 KB) |  | HTML iconHTML  

    We have developed the world's first large-scale test element group (TEG) with large-scale elements that accurately evaluate SoC (system on chip)-level yield and variation. To enable quick feedback on processing, address decoders on all four sides of the chip and testing programs were also developed. The TEG has a simple structure to examine pure (i.e., not oriented to products) logic-processes, yield and variation for near-minimum DSM (deep sub-micron) design rules. We have successfully measured yield, failure mode and locations both before and after on-chip high-voltage stress. It was also demonstrated that intra-/inter-die variations in various process/device elements could be quickly diagnosed within a week. The new TEG consists of five chips designed using 130-nm CMOS technology with 100-nm physical gate lengths and five copper interconnect layers. The proposed TEG could provide a strategic standard test structure for diagnosis of SoC yield/variation, as well as a technology standard for measuring electrical dimensions and evaluating charge-up damage. View full abstract»

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  • Infrastructure development and integration of electrical-based dimensional process window checking

    Page(s): 123 - 141
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2688 KB) |  | HTML iconHTML  

    This study aims to provide an integrated infrastructure for electrical-based dimensional process-window checking. The proposed infrastructure is comprised of design tools, testing programs, and analytical tools, providing an automatic and hierarchical test vehicle design flow from the design of the test structure to the analysis of the electrical test data. Symbolic parameter representation is adopted to describe the relationship between design rules and test structure parameters. This integrated infrastructure also provides a specific capability for controlling local/global layout geometry and pattern density, thereby fulfilling deep sub-micron design criteria. With the aid of this design platform, discrepancies between the design rule set, test structure design, and the testing plan are minimized. Using the function-independent Test Structure Design Intellectual Property ( TSD-IP) provided by this infrastructure, the process-window is quantitatively characterized as the electrical parameters. A cross-generation test vehicle (130-nm/90-nm nodes), used for evaluating any overlay shifts and variations in critical dimensions across the intra- and interphoto fields, has been developed to demonstrate the proposed design infrastructure. View full abstract»

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  • Selection and modeling of integrated RF varactors on a 0.35-μm BiCMOS technology

    Page(s): 142 - 149
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    Integrated varactors are becoming a common feature for many RF designs and in particular RF voltage controlled oscillators (VCOs). Optimization of the quality of both the inductor and the varactor from the VCO core is essential. This work details the characterization and optimization of a number of varactor types available on a typical submicron BiCMOS process. Engineering of the bottom plate of the varactor was used to optimize the quality factor of the varactor. No additional mask layers or processing steps were required to achieve this. Integrated isolated diode varactors with quality factors of 30 at 2 GHz have been demonstrated with tuning capacitance ranges of 2.5. Integrated MOS capacitor varactors with quality factors of 50 at 2 GHz have been demonstrated with tuning capacitance range of 5. A spice model for one of the varactor types is further developed in this paper. Accurate prediction of varactor performance over voltage bias and frequency was achieved. View full abstract»

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  • Test structure design considerations for RF-CV measurements on leaky dielectrics

    Page(s): 150 - 154
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB) |  | HTML iconHTML  

    We present an MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm2. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion. View full abstract»

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  • Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

    Page(s): 155 - 165
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1360 KB) |  | HTML iconHTML  

    For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 μm, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element selection and precise measurement are achieved with low parasitic resistance measurement buses and leakage-controlled switching circuits, which allow the measurement accuracy for a transistor, resistor, or capacitor of 90 pA, 11 mΩ, and 23 aF, respectively, in the 3σ range. The ability to obtain 29 008 samples from a chip enables statistical analysis of the variation in 148 elements of each chip with 240-μm spatial resolution. This high resolution and large sample number allows us to precisely decompose the data into systematic and random variation parts with newly developed fourth-order polynomial fitting. Our methodology has been verified using a test chip fabricated by a 130-nm CMOS process with a 100-nm physical gate length and five Cu interconnect layers. In MOSFETs, the random part was dominant and indicated a certain σ value in every chip. In the case of the interconnect layers, the random and systematic parts of the resistance and the capacitance indicated variance fluctuations. By chip, by item, by size, by structure, random or systematic, the σ values of each variation show inconsistency which we believe is attributable to the Cu process. The correlation coefficients of systematic part between device element and ring oscillator frequency shown very high value (0.87-0.98), and those of a random part were low enough (-0.10-0.22) to prove the accuracy of decomposition. View full abstract»

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  • Optimized overlay metrology marks: theory and experiment

    Page(s): 166 - 179
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB) |  | HTML iconHTML  

    In this paper, we provide a detailed analysis of overlay metrology mark and find the mapping between various properties of mark patterns and the expected dynamic precision and fidelity of measurements. We formulate the optimality criteria and suggest an optimal overlay mark design in the sense of minimizing the Cramer-Rao lower bound on the estimation error. Based on the developed theoretical results, a new overlay mark family is proposed-the grating marks. A thorough testing performed on the new grating marks shows a strong correlation with the underlying theory and demonstrate the superior quality of the new design over the overlay patterns used today. View full abstract»

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  • In situ endpoint detection by pad temperature in chemical-mechanical polishing of copper overlay

    Page(s): 180 - 187
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    As the number of metal levels and the wafer size increase, the global planarity and effective removal of metal overlay across the wafer becomes more crucial. Chemical-mechanical polishing (CMP) has been recognized essential to achieve this goal. Accurate in situ endpoint detection and monitoring method significantly improves the yield and throughput. Previous methods have been proposed, which either require the rearrangement of the machine set-up, or can only be implanted on certain types of machines. In this study, a model for pad temperature capable of predicting the endpoint of CMP in situ is established based on the total consumed kinematic energy between wafer and pad. Limited assumptions of thermal and kinematic conditions are made. The model of temperature rise uses the integral of the relative polishing speed and is verified by on-line measurement. Since the coefficient of friction between the pad and dielectric layer is distinguishably lower than that between the pad and the metal layer, the pad temperature increases milder than polishing the metal layer. In use of the proposed regression method applied to the measured temperature rise, the endpoint of the process can be detected. View full abstract»

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  • Simplified implementation of the windowing method for systematic and random yield calculation

    Page(s): 188 - 191
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB) |  | HTML iconHTML  

    To separate systematic and random yield loss, common implementations of the windowing method use an unweighted fit of the Poisson model. By comparison to a properly weighted fit of the negative binomial model, we show that the unweighted fit of the Poisson model can give highly inaccurate results, especially in the presence of clustering. The unweighted fit of the Poisson model is shown to improve by reducing the number of points included, with the best results given by the very simplest form, which uses two points only. View full abstract»

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  • TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling

    Page(s): 192 - 200
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB) |  | HTML iconHTML  

    The effects of line edge roughness (LER) of nanometer scale gate pattern on the MOS transistor parameter fluctuations and their technology scaling are investigated using the simplified modeling and statistical analysis based on two-dimensional technology CAD (TCAD) tools. From the simple statistical analysis, it is shown that the gate patterns without appropriate LER may cause severe device parameter and performance fluctuations in highly scaled nanometer technologies, resulting in a negative average threshold voltages shift, a subthreshold slope degradation, an unrealistic effective channel length extraction and an exponential increase in off-state leakage current due to LER-induced inhomogeneous channel potential. The characteristics of the average off-state leakage current and the threshold voltage uncertainty as a function of technology scaling provide a useful guideline for advanced gate patterning process and demand much tighter control of LER less than 3-5 nm for a successful CMOS scaling into deep nanometer scale physical gate length regime below 50 nm. View full abstract»

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  • SPICE modeling of process variation using location depth corner models

    Page(s): 201 - 213
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    For robust designs, the influence of process variations has to be considered during circuit simulation. We propose a nonparametric statistical method to find sets of simulation parameters that cover the process spread with a minimum number of simulation runs. Process corners are determined from e-test parameter vectors using a location depth algorithm. The e-test corner vectors are then transformed to SPICE parameter vectors by a linear mapping. A special corner extension algorithm makes the resulting simulation setup robust against moderate process shifts while preserving the underlying correlation structure. To be applicable in a production and circuit design environment, the models are integrated into an automated model generation flow for usage within a design-framework. The statistical methods are validated for analog/mixed-signal benchmark circuits. View full abstract»

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  • The removal of airborne molecular contamination in cleanroom using PTFE and chemical filters

    Page(s): 214 - 220
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    Cleanroom contamination and its impact on the performance of devices are beginning to be investigated due to the increasing sensitivity of the semiconductor manufacturing process to airborne molecular contamination (AMC). A clean bench was equipped with different filter modules and then most AMC in the cleanroom and in the clean bench was detected through air-sampling and wafer-sampling experiments. Additionally, the effect of AMC on device performance was examined by electrical characterization. A combination of the NEUROFINE PTFE filter and chemical filters was found to control metal, organic, and inorganic contamination. We believe that the new combination of filters can be used to improve the manufacturing environment of devices, which are being continuously shrunk to the nanometer scale. View full abstract»

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  • Real-time carbon content control for PECVD ZrO2 thin-film growth

    Page(s): 221 - 230
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    We present a methodology for real-time control of thin-film carbon content in a plasma-enhanced metal-organic chemical vapor deposition process using combination of online gas phase measurements obtained through optical emission spectroscopy and off-line (ex situ) measurements of film composition obtained via X-ray photoelectron spectroscopy (XPS). Initially, an estimation model of carbon content of ZrO2 thin films based on real-time optical emission spectroscopy data is presented. Then, a feedback control scheme, which employs the proposed estimation model and a proportional-integral controller, is developed to achieve carbon content control. Using this approach, a real-time control system is developed and implemented on an experimental electron cyclotron resonance high-density plasma-enhanced chemical vapor deposition system to demonstrate the effectiveness of real-time feedback control of carbon content. Experimental results of depositions and XPS analysis of deposited thin films under both open-loop and closed-loop operations are shown and compared. The advantages of operating the process under real-time feedback control in terms of robust operation and lower carbon content are demonstrated. View full abstract»

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  • Integrated bake/chill module with in situ temperature measurement for photoresist processing

    Page(s): 231 - 242
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB) |  | HTML iconHTML  

    Thermal processing of photoresist are critical steps in the microlithography sequence. The postexpose bake (PEB) steps for current DUV chemically amplified resists is especially sensitive to temperature variations. The problem is complicated with increasing wafer size and decreasing feature size. Conventional thermal systems are no longer able to meet these stringent requirements. The reason is that the large thermal mass of conventional hot plates prevents rapid movements in substrate temperature to compensate for real-time errors during transients. The implementation of advanced control systems with conventional technology cannot overcome the inherent operating limitation. An integrated bake/chill module with in situ temperature measurement capability has been developed for the baking of 300-mm silicon wafers. The system provides in situ sensing of the substrate temperature. Real-time closed-loop control of the substrate temperature is thus possible as oppose to conventional open-loop control of the substrate temperature. Experimental results are provided to demonstrate a complete thermal cycle. View full abstract»

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  • IEEE International Conference on Microelectronic Test Structures

    Page(s): 243
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    Freely Available from IEEE
  • IEEE 2004 International Integrated Reliability Workshop

    Page(s): 244
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    Freely Available from IEEE
  • IEEE Transactions on Semiconductor Manufacturing Information for authors

    Page(s): c3
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Anthony Muscat
Department of Chemical and Environmental Engineering
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University of Arizona
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