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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 5 • May 2004

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Displaying Results 1 - 17 of 17
  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Pulsed wave interconnect

    Publication Year: 2004, Page(s):453 - 463
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (389 KB) | HTML iconHTML

    Pulsed wave interconnect is proposed for global interconnect applications. Signals are represented by localized wave-packets that propagate along the interconnect lines at the local speed of light to trigger the receivers. Energy consumption is reduced through charging up only part of the interconnect lines and using the voltage doubling property of the receiver gate capacitances. In a 0.18-/spl m... View full abstract»

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  • Low-power on-chip communication based on transition-aware global signaling (TAGS)

    Publication Year: 2004, Page(s):464 - 476
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (485 KB) | HTML iconHTML

    In this paper, we propose a new circuit structure, the transition aware global signaling (TAGS) receiver, that detects transitions at arbitrary switch points. The major performance advantage of this circuit occurs when it switches before the 50% point in the input transition. The TAGS receiver stores the next state of the line while quiet. Upon detection of a transition at the end of the line the ... View full abstract»

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  • High-performance and low-power conditional discharge flip-flop

    Publication Year: 2004, Page(s):477 - 484
    Cited by:  Papers (61)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB) | HTML iconHTML

    In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies. This classification is based on how to prevent or reduce the redundant internal switching activities. A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional disch... View full abstract»

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  • Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

    Publication Year: 2004, Page(s):485 - 496
    Cited by:  Papers (38)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB) | HTML iconHTML

    A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off... View full abstract»

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  • Reliable low-power digital signal processing via reduced precision redundancy

    Publication Year: 2004, Page(s):497 - 510
    Cited by:  Papers (79)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (950 KB) | HTML iconHTML

    In this paper, we present a novel algorithmic noise-tolerance (ANT) technique referred to as reduced precision redundancy (RPR). RPR requires a reduced precision replica whose output can be employed as the corrected output in case the original system computes erroneously. When combined with voltage overscaling (VOS), the resulting soft digital signal processing system achieves up to 60% and 44% en... View full abstract»

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  • Systematic IEEE rounding method for high-speed floating-point multipliers

    Publication Year: 2004, Page(s):511 - 521
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (385 KB) | HTML iconHTML

    For performance reasons, many high-speed floating-point multipliers today precompute multiple significand values (SVs) in advance. The final normalization and rounding steps are then performed by selecting the appropriate SV. While having speed advantages, this integrated rounding method complicates the development of the rounding logic significantly, hence, requiring a systematic rounding method.... View full abstract»

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  • Design of low-error fixed-width modified booth multiplier

    Publication Year: 2004, Page(s):522 - 531
    Cited by:  Papers (66)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (519 KB) | HTML iconHTML

    This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quan... View full abstract»

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  • A new maximal diagnosis algorithm for interconnect test

    Publication Year: 2004, Page(s):532 - 537
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    Interconnect test for highly integrated environments becomes more important in terms of its test time and a complete diagnosis, as the complexity of the circuit increases. Since the board-level interconnect test is based on boundary scan technology, it takes a long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue. Since the board-lev... View full abstract»

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  • A low-power reduced swing global clocking methodology

    Publication Year: 2004, Page(s):538 - 545
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB) | HTML iconHTML

    In this brief, we investigate the potential of reduced swing clock networks for low-power applications. We designed and laid out a full swing conventional and a reduced swing H-tree clock distribution network in 0.13-/spl mu/m CMOS technology operating at 500 MHz. In the reduced swing clock network, the swing was reduced in the global clock distribution network and was restored to the full swing i... View full abstract»

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  • Small area parallel Chien search architectures for long BCH codes

    Publication Year: 2004, Page(s):545 - 549
    Cited by:  Papers (30)  |  Patents (70)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (165 KB) | HTML iconHTML

    To implement parallel BCH (Bose-Chaudhuri-Hochquenghem) decoders in an area-efficient manner, this paper presents a novel group matching scheme to reduce the Chien search hardware complexity by 60% for BCH(2047, 1926, 23) code as opposed to only 26% if directly applying the iterative matching algorithm. The proposed scheme exploits the substructure sharing within a finite field multiplier (FFM) an... View full abstract»

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  • IEEE International Symposium on Circuits and Systems (ISCAS 2004)

    Publication Year: 2004, Page(s): 550
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  • The 13th International Workshop on Logic & Synthesis (IWLS)

    Publication Year: 2004, Page(s): 551
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  • IEEE International Symposium on Low Power Electronics and Design (ISLPED'04)

    Publication Year: 2004, Page(s): 552
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu