IEEE Transactions on Computers

Issue 6 • June 2004

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Displaying Results 1 - 18 of 18
  • [Front cover]

    Publication Year: 2004, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2004, Page(s): c2
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  • An effective multilevel algorithm for bisecting graphs and hypergraphs

    Publication Year: 2004, Page(s):641 - 652
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1744 KB) | HTML iconHTML

    Partitioning is a fundamental problem in diverse fields of study such as data mining, parallel processing, and the design of VLSI circuits. A new approach to partition graphs and hypergraphs is introduced. This new approach combines local and global sampling, clustering, and Tabu search in a multilevel partitioning algorithm (TPART). TPART was implemented in a C program and compared to many state-... View full abstract»

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  • Complexity-effective reorder buffer designs for superscalar processors

    Publication Year: 2004, Page(s):653 - 665
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1376 KB) | HTML iconHTML

    All contemporary dynamically scheduled processors support register renaming to cope with false data dependencies. One of the ways to implement register renaming is to use the slots within the reorder buffer (ROB) as physical registers. In such designs, the ROB is a large multiported structure that occupies a significant portion of the die area and dissipates a sizable fraction of the total chip po... View full abstract»

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  • Minimal weight digit set conversions

    Publication Year: 2004, Page(s):666 - 677
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB) | HTML iconHTML

    We consider the problem of recoding a number to minimize the number of nonzero digits in its representation, that is, to minimize the weight of the representation. A general sliding window scheme is described that extends minimal binary sliding window conversion to arbitrary radix and to encompass signed digit sets. This new conversion expresses a number of known recoding techniques as special cas... View full abstract»

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  • Near optimality of Chebyshev interpolation for elementary function computations

    Publication Year: 2004, Page(s):678 - 687
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB) | HTML iconHTML

    A common practice for computing an elementary transcendental function in an libm implementation nowadays has two phases: reductions of input arguments to fall into a tiny interval and polynomial approximations for the function within the interval. Typically, the interval is made tiny enough so that polynomials of very high degree aren't required for accurate approximations. Often, approximating po... View full abstract»

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  • A comparative study of two Boolean formulations of FPGA detailed routing constraints

    Publication Year: 2004, Page(s):688 - 696
    Cited by:  Papers (39)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1136 KB) | HTML iconHTML

    We present empirical analyses of two Boolean satisfiability (SAT) formulations of FPGA (field programmable gate array) detailed routing constraints. Boolean SAT-based routing transforms a routing problem into a Boolean SAT instance by rendering geometric routing constraints as an atomic Boolean function. The generated Boolean function is satisfiable if and only if the corresponding routing is poss... View full abstract»

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  • Isolating short-lived operands for energy reduction

    Publication Year: 2004, Page(s):697 - 709
    Cited by:  Papers (8)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1456 KB) | HTML iconHTML

    A mechanism for reducing the power requirements in processors that use a separate (architectural) register file (ARF) for holding committed values is proposed. We exploit the notion of short-lived operands-values that target architectural registers that are renamed by the time the instruction producing the value reaches the writeback stage. Our simulations of the SPEC 2000 benchmarks show that as ... View full abstract»

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  • Testing layered interconnection networks

    Publication Year: 2004, Page(s):710 - 722
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1192 KB) | HTML iconHTML

    We present an approach for fault detection in layered interconnection networks (LINs). An LIN is a generalized multistage interconnection network commonly used in reconfigurable systems; the nets (links) are arranged in sets (referred to as layers) of different size. Switching elements (made of simple switches such as transmission-gate-like devices) are arranged in a cascade to connect pairs of la... View full abstract»

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  • Locality-based online trace compression

    Publication Year: 2004, Page(s):723 - 731
    Cited by:  Papers (9)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1064 KB) | HTML iconHTML

    Trace-driven simulation is one of the most important techniques used by computer architecture researchers to study the behavior of complex systems and to evaluate new microarchitecture enhancements. However, modern benchmarks, which largely resemble real-world applications, result in long and unmanageable traces. Compression techniques can be employed to reduce storage requirement of traces. Speci... View full abstract»

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  • Tolerating late memory traps in dynamically scheduled processors

    Publication Year: 2004, Page(s):732 - 743
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1064 KB) | HTML iconHTML

    In the past few years, exception support for memory functions such as virtual memory, informing memory operations, software assist for shared memory protocols, or interactions with processors in memory has been advocated in various research papers. These memory traps may occur on a miss in the cache hierarchy or on a local or remote memory access. However, contemporary, dynamically scheduled proce... View full abstract»

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  • Dynamic window-constrained scheduling of real-time streams in media servers

    Publication Year: 2004, Page(s):744 - 759
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1112 KB) | HTML iconHTML

    We describe an algorithm for scheduling packets in real-time multimedia data streams. Common to these classes of data streams are service constraints in terms of bandwidth and delay. However, it is typical for real-time multimedia streams to tolerate bounded delay variations and, in some cases, finite losses of packets. We have therefore developed a scheduling algorithm that assumes streams have w... View full abstract»

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  • Low-cost solutions for preventing simple side-channel analysis: side-channel atomicity

    Publication Year: 2004, Page(s):760 - 768
    Cited by:  Papers (80)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1136 KB) | HTML iconHTML

    We introduce simple methods to convert a cryptographic algorithm into an algorithm protected against simple side-channel attacks. Contrary to previously known solutions, the proposed techniques are not at the expense of the execution time. Moreover, they are generic and apply to virtually any algorithm. In particular, we present several novel exponentiation algorithms, namely, a protected square-a... View full abstract»

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  • a full RNS implementation of RSA

    Publication Year: 2004, Page(s):769 - 774
    Cited by:  Papers (102)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (397 KB) | HTML iconHTML

    We present the first implementation of RSA in the residue number system (RNS) which does not require any conversion, either from radix to RNS beforehand or RNS to radix afterward. Our solution is based on an optimized RNS version of Montgomery multiplication. Thanks to the RNS, the proposed algorithms are highly parallelizable and seem then well suited to hardware implementations. We give the comp... View full abstract»

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  • Compact dictionaries for fault diagnosis in scan-BIST

    Publication Year: 2004, Page(s):775 - 780
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB) | HTML iconHTML

    We present a new technique for generating compact dictionaries for cause-effect fault diagnosis in scan-BIST. This approach relies on the use of three compact dictionaries: 1) D1, containing compacted LFSR signatures for a small number of patterns and faults with high detection probability, 2) an interval-based pass/fail dictionary D2 for the BIST patterns and for faults with... View full abstract»

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  • Optimal utilization bounds for the fixed-priority scheduling of periodic task systems on identical multiprocessors

    Publication Year: 2004, Page(s):781 - 784
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    In fixed-priority scheduling, the priority of a job,.once assigned, may not change. A new fixed-priority algorthm for scheduling systems of periodic tasks upon identical multiprocessors is proposed. This algorithm has an achievable utilization of (m+1)/2 upon m unit-capacity processors. It is proven that this algorithm is optimal from the perspective of achievable utilization in the sense that no ... View full abstract»

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  • TC Information for authors

    Publication Year: 2004, Page(s): c3
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  • [Back cover]

    Publication Year: 2004, Page(s): c4
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org