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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 3 • March 2004

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Displaying Results 1 - 21 of 21
  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Guest Editorial

    Publication Year: 2004, Page(s):233 - 234
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  • Power-delay product minimization in high-performance 64-bit carry-select adders

    Publication Year: 2004, Page(s):235 - 244
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (450 KB) | HTML iconHTML

    This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18-/spl mu/m partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay of 720 ps and a power dissipation of 96 mW at 1.5 V. The reduction of the stack height in the... View full abstract»

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  • DCG: deterministic clock-gating for low-power microprocessor design

    Publication Year: 2004, Page(s):245 - 254
    Cited by:  Papers (29)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB) | HTML iconHTML

    With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Because clock power can be significant in high-performance processors, we propose a deterministic clock-gating (DCG) technique which effectively reduces clock power. DCG is based on the key observation that for many of the pipelined... View full abstract»

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  • Memory energy minimization by data compression: algorithms, architectures and implementation

    Publication Year: 2004, Page(s):255 - 268
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (629 KB) | HTML iconHTML

    Storing data in compressed form is becoming common practice in high-performance systems, where memory bandwidth constitutes a serious bottleneck to program execution speed. In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of processor-based systems. We propose a novel and efficient architecture for on-the-fly data compression and decompression ... View full abstract»

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  • Memory-access-aware data structure transformations for embedded software with dynamic data accesses

    Publication Year: 2004, Page(s):269 - 280
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB) | HTML iconHTML

    Embedded systems are evolving from traditional, stand-alone devices to devices that participate in Internet activity. The days of simple, manifest embedded software [e.g. a simple finite-impulse response (FIR) algorithm on a digital signal processor (DSP] are over. Complex, nonmanifest code, executed on a variety of embedded platforms in a distributed manner, characterizes next generation embedded... View full abstract»

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  • Compiler-directed scratch pad memory optimization for embedded multiprocessors

    Publication Year: 2004, Page(s):281 - 287
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB) | HTML iconHTML

    This paper presents a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets at reducing extra off-chip memory accesses caused by interprocessor communication. This is achieved by increasing the application-wide reuse of data that resides in scratch-pad memo... View full abstract»

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  • The effect of LUT and cluster size on deep-submicron FPGA performance and density

    Publication Year: 2004, Page(s):288 - 298
    Cited by:  Papers (130)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (557 KB) | HTML iconHTML

    In this paper, we revisit the field-programmable gate-array (FPGA) architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cluster-based island-style FPGAs (Betz et al. 1997) we look at the effect of lookup table (LUT) size and cluster size (number of LUTs per cluster) on the speed and logic density of an FPGA. ... View full abstract»

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  • Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits

    Publication Year: 2004, Page(s):299 - 311
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (403 KB) | HTML iconHTML

    High fault tolerance for transient faults and low-power consumption are key objectives in the design of critical embedded systems. Systems like smart cards, PDAs, wearable computers, pacemakers, defibrillators, and other electronic gadgets must not only be designed for fault tolerance but also for ultra-low-power consumption due to limited battery life. In this paper, a highly accurate method of e... View full abstract»

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  • Overview of a compiler for synthesizing MATLAB programs onto FPGAs

    Publication Year: 2004, Page(s):312 - 324
    Cited by:  Papers (19)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (610 KB) | HTML iconHTML

    This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of digital signal processing (DSP) applications written in MATLAB, and automatically generates synthesizable register transfer level (RTL) models and simulation testbenches in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools ont... View full abstract»

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  • A CAM with mixed serial-parallel comparison for use in low energy caches

    Publication Year: 2004, Page(s):325 - 329
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (239 KB) | HTML iconHTML

    A novel, low-energy content addressable memory (CAM) structure is presented which achieves an approximately four-fold improvement in energy per access, compared to a standard parallel CAM, when used as tag storage for caches. It exploits the address patterns commonly found in application programs, where testing the four least significant bits of the tag is sufficient to determine over 90% of the t... View full abstract»

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  • IEEE International Symposium on Circuits and Systems (ISCAS 2004)

    Publication Year: 2004, Page(s): 330
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  • The 13th International Workshop on Logic & Synthesis (IWLS)

    Publication Year: 2004, Page(s): 331
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  • IEEE International Symposium on Low Power Electronics and Design (ISLPED'04)

    Publication Year: 2004, Page(s): 332
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  • 11th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2004)

    Publication Year: 2004, Page(s): 333
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  • IEEE Member Digital Library [advertisement]

    Publication Year: 2004, Page(s): 334
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  • Join IEEE

    Publication Year: 2004, Page(s): 335
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  • Leading the field since 1884 [advertisement]

    Publication Year: 2004, Page(s): 336
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu