IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • April 2004

Filter Results

Displaying Results 1 - 20 of 20
  • Table of contents

    Publication Year: 2004, Page(s): c1
    Request permission for commercial reuse | |PDF file iconPDF (41 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2004, Page(s): c2
    Request permission for commercial reuse | |PDF file iconPDF (37 KB)
    Freely Available from IEEE
  • Guest Editorial

    Publication Year: 2004, Page(s):449 - 450
    Request permission for commercial reuse | |PDF file iconPDF (55 KB) | HTML iconHTML
    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Repeater scaling and its impact on CAD

    Publication Year: 2004, Page(s):451 - 463
    Cited by:  Papers (64)  |  Patents (71)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (664 KB) | HTML iconHTML

    We study scaling in the context of typical block-level wiring distributions, and identify its impact on the design process. In particular, we study the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for physical synthesis and full-chip assembly, showing that mere capacity scaling of current algorithms and methodologies is insu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning

    Publication Year: 2004, Page(s):464 - 471
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (352 KB) | HTML iconHTML

    Traditional multilevel partitioning approaches have shown good performance with respect to cutsize, but offer no guarantees with respect to system performance. Timing-driven partitioning methods based on iterated net reweighting, partitioning, and timing analysis have been proposed (Ababei et al., 2002), as well as methods that apply degrees of freedom such as retiming (Cong et al., 2000), (Cong e... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Benchmarking for large-scale placement and beyond

    Publication Year: 2004, Page(s):472 - 487
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1176 KB) | HTML iconHTML

    Over the last five years, the large scale integrated circuit placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results. These advances have been supported by a nontrivial benchmarking infrastructure, and future achievements are set to draw on benchmarking as well. In this paper, we rev... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Crosstalk noise control in an SoC physical design flow

    Publication Year: 2004, Page(s):488 - 497
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (360 KB) | HTML iconHTML

    Signal integrity closure is one of the key challenges in deep submicron physical design. In this paper, we propose a physical design methodology which includes signal integrity management through crosstalk noise analysis and repair at multiple phases of the design so that a quick noise convergence can be achieved. The methodology addresses both functional and delay noise problems in the design and... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Equivalent waveform propagation for static timing analysis

    Publication Year: 2004, Page(s):498 - 508
    Cited by:  Papers (10)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (688 KB) | HTML iconHTML

    This paper proposes a scheme that captures diverse input waveforms of CMOS gates for static timing analysis (STA). Conventionally latest arrival and transition times are calculated from the timings when a transient waveform goes across predetermined reference voltages. However, this method cannot accurately consider the impact of waveform shape on gate delay when crosstalk-induced nonmonotonic wav... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees

    Publication Year: 2004, Page(s):509 - 516
    Cited by:  Papers (30)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (280 KB) | HTML iconHTML

    Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these formulae assume a step excitation, leaving it to the reader to find a suitable extension to ramp-we always refer to saturated ramps in this paper-inputs. The few works that do consider ramp inputs do not present a closed-... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Porosity-aware buffered Steiner tree construction

    Publication Year: 2004, Page(s):517 - 526
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (784 KB) | HTML iconHTML

    In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis system. Modern designs may contain large blocks which severely constrain the buffer locations. Even when there may appear to be space for buffers in the alleys between large blocks, these regions are often densely packed or may b... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fine granularity clustering-based placement

    Publication Year: 2004, Page(s):527 - 536
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (344 KB) | HTML iconHTML

    In this paper, we address the problem of improving the efficiency of placement algorithms. We employ a fine granularity clustering technique to reduce the original placement problem size. The reduction is feasible because a global placer may not need to operate on the bottom level netlist in order to achieve a competitive result. In general, placement algorithm efficiency is well correlated with t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimality and scalability study of existing placement algorithms

    Publication Year: 2004, Page(s):537 - 549
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (928 KB) | HTML iconHTML

    Placement is an important step in the overall IC design process in deep submicron technologies, as it defines the on-chip interconnects which have become the bottleneck in determining circuit performance. The rapidly increasing design complexity, combined with the demand for the capability of handling nearly flattened designs for physical hierarchy generation, poses significant challenges to exist... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Architecture and synthesis for on-chip multicycle communication

    Publication Year: 2004, Page(s):550 - 564
    Cited by:  Papers (40)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (992 KB) | HTML iconHTML

    For multigigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register (RDR) microarchitecture, which offers high regularity and direct support of multicycle on-chip communication. The RDR microarchitecture divides the entire chip into an array of islands so that all local computation and com... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing

    Publication Year: 2004, Page(s):565 - 572
    Cited by:  Papers (34)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (528 KB) | HTML iconHTML

    Clock distribution is crucial for timing and design convergence in high-performance very large scale integration designs. Minimum-delay/power zero skew buffer insertion/sizing and wire-sizing problems have long been considered intractable. In this paper, we present ClockTune , a simultaneous buffer insertion/sizing and wire-sizing algorithm which guarantees zero skew and minimizes delay and power ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Constrained floorplanning using network flows

    Publication Year: 2004, Page(s):572 - 580
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (656 KB) | HTML iconHTML

    This paper presents algorithms for a constrained version of the "modern" floorplanning problem proposed by Kahng in "Classical Floorplanning Harmful?" (Kahng, 2000). Specifically, the constrained modern floorplanning problem (CMFP) is suitable when die-size is fixed, modules are permitted to have rectilinear shapes and, in addition, the approximate relative positions of the modules are known. This... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Corrections to “Physically Rigorous Modeling of Internal Laser-Probing Techniques for Microstructured Semiconductor Devices”

    Publication Year: 2004, Page(s):581 - 582
    Cited by:  Papers (1)
    Request permission for commercial reuse | |PDF file iconPDF (91 KB) | HTML iconHTML
    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 2004 IEEE Asia-Pacific Conference on Circuits and Systems

    Publication Year: 2004, Page(s): 583
    Request permission for commercial reuse | |PDF file iconPDF (156 KB)
    Freely Available from IEEE
  • 2004 IEEE International Workshop on Behavioral Modeling and Simulation (BMAS 2004)

    Publication Year: 2004, Page(s): 584
    Request permission for commercial reuse | |PDF file iconPDF (155 KB)
    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2004, Page(s): c3
    Request permission for commercial reuse | |PDF file iconPDF (34 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2004, Page(s): c4
    Request permission for commercial reuse | |PDF file iconPDF (23 KB) | HTML iconHTML
    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu