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Selected Areas in Communications, IEEE Journal on

Issue 5 • Date Jun 1991

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Displaying Results 1 - 16 of 16
  • A Si-bipolar technology for optical fiber transmission rates above 10 Gb/s

    Publication Year: 1991 , Page(s): 652 - 655
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    A multiplexer operating at up to 12 Gb/s has been demonstrated using a simple, but optimized, silicon bipolar technology with 2 μm lithography. Using this simple but optimized technology, a 12 Gb/s multiplexer was implemented. Circuit simulations predict the increase of the bit rate up to at least 15 Gb/s by changing to the 1.5 μm lithography. The results of experimental investigations and circuit simulations show that low-cost silicon-based bipolar circuits will be available for future optical-fiber transmission systems with data rates higher than 10 Gb/s View full abstract»

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  • Multi-Gb/s silicon bipolar clock recovery IC

    Publication Year: 1991 , Page(s): 656 - 663
    Cited by:  Papers (11)  |  Patents (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    A novel clock recovery IC for optical fiber communication systems with data rates up to several Gb/s is presented. It combines nonlinear signal preprocessing directly with a regenerative frequency divider scheme and an external filter in the divider loop. Hence, the center frequency of the filter and the working frequency of the amplifier are halved. The extracted clock frequency corresponds to half the bit rate, as required for many clocked circuit components within fiber optic lines. Two versions of the same IC design, scheduled for two bit rate ranges between 0.3-4 Gb/s, are realized with a conventional Si bipolar process. Clock recovery is demonstrated at 2.2 and 3.52 Gb/s, using both cavity and surface acoustic wave (SAW) filters View full abstract»

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  • Techniques for high-speed implementation of nonlinear cancellation

    Publication Year: 1991 , Page(s): 711 - 717
    Cited by:  Papers (67)  |  Patents (68)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    The authors present techniques for breaking the bottleneck caused by delays in the feedback loop, which can severely limit the maximum data rate of a detector, operating with nonlinear cancellation (NLC). The authors first show how to simplify the loop to avoid high-speed switching of analog signals by using multiple decision elements, each with a different threshold level. The authors then show how to use lookahead computation to increase the delay permissible in the feedback loop. The authors describe nonlinear cancellation, and outline some of the problems of implementing NLC at high data rates. Techniques for overcoming these problems are developed and are illustrated with the example of a simple one-tap NLC. The authors describe how to generalize the techniques to more complex NLCs and present some more examples View full abstract»

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  • Architectural techniques for eliminating critical feedback paths

    Publication Year: 1991 , Page(s): 718 - 725
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (748 KB)  

    The authors demonstrate architectural techniques, for small-state feedback circuits that significantly improve the throughput without requiring circuit design efforts or advanced technologies. The method is flexible in terms of achievable implementations and speedups. The authors discuss a new high-throughput solution for systems with finite-level feedback values. As an example, the authors consider coding and signal processing systems for optical communications, which usually have very simple feedback. The authors demonstrate the method by realizing a 2 micron CMOS layout of a bimode 3B4B line coder. Simulation results show that, using standard cell design, the chip achieves a coding rate of 1.4 Gb/s. Other design options are discussed View full abstract»

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  • All-silicon integrated optical modulator

    Publication Year: 1991 , Page(s): 704 - 710
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB)  

    The authors describe the operating principle, design, and performance of an all-silicon light modulator at 1.3 μm wavelength. The modulator is based on the plasma effect in silicon and the mode selectivity of single-mode optical fibers, resulting in low polarization dependence and the capability of handling high light intensities. Standard silicon IC technology is used in the fabrication process and the modulator has a vertical structure that takes up a small surface area (the active area matches the single-mode fiber core of 9 μm diameter), simplifying integration with other circuitry on the same chip. The modulator can be directly coupled to a single-mode optical fiber, without using lenses or other bulk optical components. Typical performance of the fabricated modulators is 6 dB insertion loss, 24% modulation depth, and 60 MHz bandwidth with a current drive of 22 mA rms View full abstract»

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  • A silicon bipolar chipset for fiber-optic applications to 2.5 Gb/s

    Publication Year: 1991 , Page(s): 664 - 672
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (904 KB)  

    A silicon bipolar chip set for fiber-optic applications to 2.5 Gb/s, which consists of a transimpedance amplifier (TZA), a decision circuit (DEC), and a laser-diode driver (LDD), is presented. The TZA has 1.7 GHz bandwidth with 3.5 pA/√Hz equivalent input-current noise. The topology consists of a Darlington input stage and a class AB output stage. The laser-diode driver functions up to a 1.5 Gb/s data rate with 50 mA modulation and 50 mA prebias current levels. The decision circuit works up to a 2.5 Gb/s data rate, with 10 mVpp input sensitivity. All the integrated circuits operate from a single 5 V power supply. A minimum of external components are required. A nonpolysilicon-emitter production process is used, with a minimum 20×30 mil die size View full abstract»

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  • Over 10 Gb/s regenerators using monolithic ICs for lightwave communication systems

    Publication Year: 1991 , Page(s): 673 - 682
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB)  

    The design and performance of repeater circuits based on Si and GaAs MESFET process technologies are described. Repeater circuits were designed and fabricated for around 10 Gb/s repeater systems using Si and GaAs IC processes. The Si ICs operated up to 9 Gb/s, and the GaAs ICs exceeded 10 Gb/s. It was verified that regenerative repeater systems using these ICs and optical amplifiers exhibit a stable operation at 10 Gb/s. The performance of the 10 Gb/s repeater using these monolithic ICs and photonic circuits is discussed View full abstract»

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  • High-speed Si-bipolar IC design for multi-Gb/s optical receivers

    Publication Year: 1991 , Page(s): 645 - 651
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    The authors developed several special circuits to minimize the decrease in speed caused by parasitics. The common-base circuit assures flat and wide frequency preamplifier response even when Vee is unstable because of bond wire inductance. Cascode interconnections between circuit blocks prevent waveform degradation due to line capacitance discharge. The high level of integration prevents the signal speed from decreasing due to chip interfaces and external interference. Using these circuits and Si-bipolar ESPER (emitter-base self-aligned structure with polysilicon electrodes and resistors) transistors whose fT was 28 GHz, the authors fabricated three ICs: a preamplifier with a 5.1 GHz bandwidth, a fully integrated automatic gain control (AGC) amplifier with a 3.6 GHz bandwidth, and a decision circuit that operates at 10.6 Gb/s. The authors used these ICs and an avalanche photodiode (APD) to construct a 5 Gb/s optical receiver with a minimum detectable optical power of -26.8 dBm. The speed of the Si ICs exceeded 5 Gb/s View full abstract»

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  • High-speed optical transmission systems using advanced monolithic IC technologies

    Publication Year: 1991 , Page(s): 683 - 688
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    The authors discuss the design and performance of monolithic ICs for multigigabit lightwave transmission systems including direct detection and coherent detection. The required function and performance of a lightwave transmitter and receiver are discussed. The fabricated ICs and their application to the transmission system are shown in a direct system. Microwave monolithic ICs for lightwave heterodyne detection and an interconnection technique are introduced. Future trends of ICs are discussed View full abstract»

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  • A 1.5 Gb/s link interface chipset for computer data transmission

    Publication Year: 1991 , Page(s): 698 - 703
    Cited by:  Papers (14)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    The authors designed a set of four ICs to provide encoding, multiplexing, clock extraction/demultiplexing, and decoding for gigabit-rate serial data transmission. These chips form a high bandwidth data link for point-to-point communication. A new line code is implemented that provides DC balance, efficient encoding, framing, and simple clock extraction. Embedded in the code is a fixed transition used by the phase/frequency locked loop (PLL) for simple clock extraction and frame synchronization. Unlike other links, this PLL requires no trimming for data retiming, either in production or later. An on-chip voltage-controlled oscillator (VCO) with a tuning range of 1.1-1.6 GHz is available for use with the PLL. With this chip set the authors demonstrated a transmission rate of 16 bits in parallel at 75 MHz or, with encoding overhead, a serial rate of 1.5 Gb/s View full abstract»

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  • Silicon bipolar integrated circuits for multi-Gb/second optical communication systems

    Publication Year: 1991 , Page(s): 636 - 644
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (856 KB)  

    The authors discuss several important circuits for fiber-optic transmission, implemented in an advanced silicon bipolar integrated circuit technology. Specifically, the authors discuss the design considerations and measured performance of a 2:1 multiplexer, front end receiver, limiting amplifier, and decision circuit IC. Also discussed are three hybrid circuit modules: a 2:1 multiplexer, 1:2 demultiplexer, and parallel processing decision circuit. These ICs and hybrid circuit modules operate at multi-Gb/s data rates. The performance of these ICs indicates that advanced silicon bipolar integrated circuits with their high speed, functionality and low cost potential could play an important role in alleviating the electronic bottleneck in future multigigabit optical communication systems View full abstract»

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  • A gigabit-rate five-highway GaAs OE-LSI chipset for high-speed optical interconnections between modules or VLSIs

    Publication Year: 1991 , Page(s): 689 - 697
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    A gigabit-rate five highway interface GaAs optoelectronic LSI chipset has been fabricated for the 0.85 μm wavelength range optical interconnections between modules or VLSIs. The optical sender consists of a high-speed laser driver array LSI having 2 Gb/s maximum operation speed and a tiny laser array. The optical receiver in a GsAs high-speed optical receiver array LSI with a monolithically integrated metal-semiconductor-metal (MSM) photodetector, a high-speed preamplifier, and a decision circuit that has a maximum operation speed of 1.8 Gb/s. The receiver LSI is provided with a new bit-synchronizing circuit and an automatic threshold determination circuit View full abstract»

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  • 2.488 Gb/s SONET multiplexer/demultiplexer with frame detection capability

    Publication Year: 1991 , Page(s): 726 - 731
    Cited by:  Papers (16)  |  Patents (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    The authors describe a novel scheme that allows a demultiplexer, a byte aligner, and a frame detection circuit tube to be integrated on one chip without compromising the demultiplexer's performance. A research prototype integrated circuit (IC) that incorporates this scheme was designed to operate at speeds up to the SONET STS-48 (synchronous transport signal level 48) rate of 2.488 Gb/s. The IC is implemented in GaAs enhancement/depletion mode MESFET technology, and it performs 1:8 demultiplexing, byte alignment, and SONET frame detection functions. A separate IC that performs 8:1 multiplexing was also implemented using the same technology. The bit error rate; test results show that the multiplexer and demultiplexer with frame detector can operate at 2.488 Gb/s with a bit error rate less than 1×10-14. Both ICs were tested at data rates up to 3 Gb/s View full abstract»

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  • Implementation of a 16 to 16 switching element for ATM exchanges

    Publication Year: 1991 , Page(s): 751 - 757
    Cited by:  Papers (6)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    The authors describe the implementation of an asynchronous transfer mode (ATM) switching element with 16 inlets and 16 outlets at 600 Mb/s each. The single board switching element is used as a basic switching block in a connection-oriented ATM switching network. The design of the switching element was carried out by using advanced BiCMOS technologies. It is shown how the functional scheme is translated into a feasible chip partitioning and which design options were taken. In particular, the design of the cell switching facility and the queueing memory is treated in detail. A comparison between memory pooling or individual output queues is presented. By making the choice of the latter solution, the development schedule could be kept very tight. Second, the testability of the chips remains good despite the high gate complexity View full abstract»

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  • The ATM layer chip: an ASIC for B-ISDN applications

    Publication Year: 1991 , Page(s): 741 - 750
    Cited by:  Papers (17)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB)  

    The authors describe the architecture of an experimental research prototype application specific integrated circuit (ASIC) designed to serve as a generic building block of the future broadband integrated services digital network (B-ISDN). The chip performs common asynchronous transfer mode (ATM) layer functions such as cell assembly and cell disassembly. A new media access control (MAC) protocol developed for a broadband customer premises network is also integrated in the chip. The chip interfaces to the B-ISDN through a synchronous optical network (SONET) synchronous transmission signal-3c (STS-3c) framer chip. The ATM layer chip has been designed using 1.2 μm CMOS technology with a die area of 5.4×5.4 mm2 and approximately 27000 transistors. Experimental results are described. At the user network interface, the chip can be used to implement broadband terminal adaptors and the network termination. At the broadband local exchange, the chip can be used in the implementation of ATM statistical multiplexers, ATM switch port controllers, etc View full abstract»

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  • A SONET STS-3c user network interface integrated circuit

    Publication Year: 1991 , Page(s): 732 - 740
    Cited by:  Papers (12)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    Two different design implementation techniques were used to produce a functionally complex high performance synchronous optical network (SONET) synchronous transmission signal (STS)-3c (155.52 Mb/s) user network interface (UNI) chip in cost-effective 1 μm CMOS technology. The CMOS chip functions as an STS-3c transmitter and receiver and can interface to the STS-3c line in either bit-serial or byte-parallel data format. The transmitter creates a SONET STS-3c frame structure including the necessary framing and control bytes. The receiver performs frame detection, several performance monitoring functions, and payload processor interpretation. In addition to SONET overheads, both the transmitter and receiver provide payload asynchronous transfer mode (ATM) mapping signals to the user. The user can choose between serial operation at 155.52 Mb/s or parallel operation at 19.44 Mbyte/s. Test results show that the experimental integrated circuit performs successfully at serial data rates of up to 300 Mb/s View full abstract»

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Aims & Scope

IEEE Journal on Selected Areas in Communications focuses on all telecommunications, including telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation.

Full Aims & Scope

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Editor-in-Chief
Muriel Médard
MIT