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Electron Devices, IEEE Transactions on

Issue 4 • Date April 2004

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Displaying Results 1 - 25 of 26
  • Table of contents

    Page(s): c1 - c4
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  • IEEE Transactions on Electron Devices publication information

    Page(s): c2
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  • Design optimization of AlInAs-GaInAs HEMTs for high-frequency applications

    Page(s): 521 - 528
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    By using a Monte Carlo simulator, the static and dynamic characteristics of 50-nm-gate AlInAs-GaInAs δ-doped high-electron mobility transistors (HEMTs) are investigated. The Monte Carlo model includes some important effects that are indispensable when trying to reproduce the real behavior of the devices, such as degeneracy, presence of surface charges, T-shape of the gate, presence of dielectrics, and contact resistances. Among the large quantity of design parameters that enter the fabrication of the devices, we have studied the influence on their performance of two important factors: the doping level of the δ-doped layer, and the width of the devices. We have confirmed that the value of the δ-doping must be increased to avoid the reduction of the drain current due to the depletion of the channel by the surface potential. However, a higher δ-doping has the drawback that the frequency performance of the HEMTs is deteriorated, and its value must be carefully chosen depending on the system requirements in terms of delivered power and frequency of operation. The reduction of the device width has been also checked to improve the cutoff frequencies of the HEMTs, with a lower limit imposed by the degradation provoked by the offset extrinsic capacitances. View full abstract»

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  • Thermal limitations of InP HBTs in 80- and 160-gb ICs

    Page(s): 529 - 534
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    Bipolar transistor scaling laws indicate that the dissipated power per unit collector-junction area increases in proportion to the square of the transistor bandwidth, increasing to ∼106 W/cm2 for InP heterojunction bipolar transistors (HBTs) designed for 160 Gb/s operation. A verified three-dimensional finite-element thermal model has been used to analyze the thermal resistance of InP in the context of 80 and 160 Gb-1 integrated circuits. The simulations show that the maximum temperature in the device can be significantly higher than the experimentally determined base-emitter junction temperature. Devices suitable for 160-Gb/s circuits will be thermally possible if the InGaAs etch-stop or contacting layer is removed from the subcollector. View full abstract»

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  • Self-consistent transit-time model for a resonant tunnel diode

    Page(s): 535 - 541
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    We present a self-consistent compact model for the small-signal impedance of a resonant tunnel diode (RTD) with a finite collector transit time. The effect of the collector transit time on the device impedance is described for three In0.53Ga0.47AsAlAs-InAs RTDs with current densities ranging from 14 kA/cm2 to 570 kA/cm2 with various collector spacer lengths for dc biasing in both the positive and negative differential resistance regions. View full abstract»

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  • Characteristics of a new BBOS with an AlGaAs-δ(n+)-GaAs-InAlGaP collector structure

    Page(s): 542 - 547
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    Two-terminal switching performances are observed in a new AlGaAs-GaAs-InAlGaP npn bulk-barrier optoelectronic switch (BBOS) with an AlGaAs-δ(n+)-GaAs-InAlGaP collector structure. The device shows that the switching action takes place from a low-current state to a high-current state through a region of negative differential resistance (NDR). The transition from either state to the other may be induced by an appropriate optical or electrical input. It is seen that the effect of illumination increases the switching voltage Vs, holding voltage VH, and holding current IH, and decreases the switching current IS, which is quite different from other results reported. In addition, it possesses obvious NDR even up to 160°C. This high-temperature performance provides the studied device with potential high-temperature applications. View full abstract»

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  • A driving method for high-speed addressing in an AC PDP using priming effect

    Page(s): 548 - 553
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    A novel driving method is proposed to reduce the addressing time in an ac plasma display panel. In this method, priming discharges are used to achieve high-speed addressing without adding an auxiliary electrode. Some of the scan lines were used to provide the priming particles for the reduction of the address discharge time lag (td) in the adjacent scan lines. The number of priming electrodes was optimized and two different types of priming discharge were tested in order to reduce the inherent light output caused by the priming discharges. In the panel experiment, the td was reduced to one half of that of the conventional method when the priming particles were provided and the background luminance was reduced from 4.97 to 2.94 cd/m2 through the reduction of the number of priming electrodes, and further, by changing the type of the priming discharge while the peak luminance could be improved more than twice by allocating the saved-time-to-display period, which in turn, resulted in a higher contrast ratio. View full abstract»

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  • Effect of mobile charge on hot-carrier degradation in lateral diffused MOSFET

    Page(s): 554 - 559
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    Hot carrier-induced device degradation in n-type lateral diffused MOSFETs with mobile charges in gate oxide has been studied. Abnormal decrease-then-increase in Vth during hot-carrier stress was observed. The decrease was found to be caused by movement of mobile charges while the increase was the normally observed hot-electron degradation. The hot-electron degradation was drastically accelerated with the presence of mobile charges and easily recovered after baking or negative gate bias. The magnitude of degradation linearly increases with mobile charge density. The acceptable limits of mobile charge density have been estimated. The observed behaviors are very similar to positive charging processes found in other n-MOSFETs that were attributed to hot-hole effects, suggesting mobile charge induced degradation must be carefully excluded in hot-hole injection studies. View full abstract»

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  • Sequential lateral solidification processing for polycrystalline Si TFTs

    Page(s): 560 - 568
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    The sequential lateral solidification (SLS) process is an excimer-laser projection-based scheme for crystallization of thin films on amorphous substrates. This method can be used to readily produce a wide range of microstructures through manipulation of grain boundary placement within the crystallized material. In this paper, we focus on the 2-shot SLS process for crystallization of thin Si films for thin-film transistor (TFT) applications. We have investigated the effect of process parameter variation on the resulting microstructure, as well as on the performance of TFTs fabricated on the material. The 2-shot SLS microstructure was further engineered to reduce anisotropy of the TFT performance relative to the lateral growth direction using additional laser scans. Through this method, we were able to improve the mobility directionality ratio between devices with majority carrier flow parallel and perpendicular to the lateral growth direction, respectively, from 0.3 to over 0.7. Post-SLS process thinning and planarization of the Si surface was used to improve the uniformity and performance of the TFT devices. View full abstract»

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  • Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

    Page(s): 569 - 574
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    A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations. View full abstract»

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  • Direct tunneling-induced floating-body effect in 90-nm pseudo-kink-free PD SOI pMOSFETs with DTMOS-like behavior and low input power consumption

    Page(s): 575 - 580
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    This paper reports the investigation of the direct tunneling-induced floating-body effect in 90-nm H-gate floating body partially depleted (PD) silicon-on-insulator (SOI) pMOSFETs with dynamic-threshold MOS (DTMOS)-like behavior and low input power consumption. Based on this paper, with the decrease of the gate-oxide thickness, the direct-tunneling current will dominate the floating body potential of H-gate PD SOI pMOSFETs, which makes the floating body potential highly gate voltage dependent like DTMOS behavior with a larger drain current. However, the input power consumption is still kept lower. Simultaneously, the highly gate voltage dependent direct-tunneling current will reduce the influence of the impact ionization current on the neutral region with a higher kink onset-voltage. It contributes to the pseudo-kink-free phenomenon in 90-nm H-gate floating body PD SOI pMOSFETs. View full abstract»

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  • The effect of annealing temperatures on self-aligned replacement (damascene) TaCN-TaN-stacked gate pMOSFETs

    Page(s): 581 - 586
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    In this paper, we report the first self-aligned replacement (Damascene) TaCN-TaN-stacked gate electrode pMOSFETs. The high-temperature (>1000°C) implant activation anneal was done prior to the metal electrode deposition. After the fabrication was completed, the transistors were then annealed at lower temperatures (300°C-600°C), which might affect the critical device parameters, such as subthreshold slope, threshold voltage, gate leakage, on, and off currents. Our data show that TaCN is a promising material for the metal-gate pMOSFETs due to the suitable metal work function and good thermal stability up to 500°C, which is much higher than the highest temperature required by the backend very large-scale integration process. View full abstract»

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  • A compact threshold voltage model for gate misalignment effect of DG FD SOI nMOS devices considering fringing electric field effects

    Page(s): 587 - 596
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    This paper reports an analysis of gate misalignment effect on the threshold voltage of double-gate ultrathin fully depleted silicon-on-insulator nMOS devices using a compact model considering the fringing electric field effect, biased at zero-bias VDS. Using the conformal mapping transformation approach, a closed-form compact model considering the fringing electric field effect in the nongate overlap region has been derived to provide an accurate prediction of the threshold voltage behavior as verified by the two-dimensional simulation results. View full abstract»

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  • A novel MONOS-type nonvolatile memory using high-κ dielectrics for improved data retention and programming speed

    Page(s): 597 - 602
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    This paper presents a novel metal-oxide-nitride-oxide-silicon (MONOS)-type nonvolatile memory structure using hafnium oxide (HfO2) as tunneling and blocking layer and tantalum pentoxide (Ta2O5) as the charge trapping layer. The superiorities of such devices to traditional SiO2-Si3N4-SiO2 stack devices in obtaining a better tradeoff between faster programming and better retention are illustrated based on a band engineering analysis. The experimental results demonstrate that the fabricated devices can be programmed as fast as 1 μs and erased from 10 ns at an 8-V gate bias. The retention decay rate of this device is improved by a factor more than three as compared to the conventional MONOS/SONOS type devices. Excellent endurance and read disturb performance are also demonstrated. View full abstract»

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  • Real impact of dynamic operation stress during burn-in on DRAM retention time

    Page(s): 603 - 608
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    The burn-in (BI) mechanism in connection with the dynamic operation stress (DOS) has been investigated to examine the real impact on dynamic random access memory (DRAM) reliablity. In this paper, the wafer burn-in (WBI) method with equivalent screening efficiency as the package burn-in (PBI) is implemented by employing DOS. It is found that retention time degradation by BI stress in DRAM with potentially lethal defects is mainly attributed to DOS-induced hot carrier (HC) degradation of DRAM cell. Hot electrons injection in Si-SiO2 interface brings about lots of interfacial states as well as the electrical field modification at the gate-overlapped region, causing the degradation of retention time. This is clarified by an anomalous threshold voltage (VT) shift, and an increase of gate-induced drain leakage (GIDL) after dc HC stress having the identical stress voltage as DOS. Moreover, it is proved that a WBI procedure with the relevant DOS can screen out weak bits effectively, compared to that with only static stress. View full abstract»

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  • Thermally robust HfN metal as a promising gate electrode for advanced MOS device applications

    Page(s): 609 - 615
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    A systematic study of thermally robust HfN metal gate on conventional SiO2 and HfO2 high-κ dielectrics for advanced CMOS applications is presented. Both HfN-SiO2 and HfN-HfO2 gate stacks demonstrates robust resistance against high-temperature rapid thermal annealing (RTA) treatments (up to 1000°C), in terms of thermal stability of equivalent oxide thickness (EOT), work function, and leakage current. This excellent property is attributed to the superior oxygen diffusion barrier of HfN as well as the chemical stability of HfN-HfO2 and HfN-SiO2 interfaces. For both gate dielectrics, HfN metal shows an effective mid-gap work function. Furthermore, the EOT of HfN-HfO2 gate stack has been successfully scaled down to less than 10 Å with excellent leakage, boron penetration immunity, and long-term reliability even after 1000°C annealing, without using surface nitridation prior to HfO2 deposition. As a result, the mobility is improved significantly in MOSFETs with HfN-HfO2 gate stack. These results suggest that HfN metal electrode is an ideal candidate for ultrathin body fully depleted silicon-on-insulator (SOI) and symmetric double-gate MOS devices. View full abstract»

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  • Analysis of transient response and operating speed of MOBILE

    Page(s): 616 - 622
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    To clarify the relationship between the figures-of-merit of resonant tunneling diodes and the operating speed of a monostable-bistable transition logic element (MOBILE), we investigated the transient response of a MOBILE using a simple current-voltage characteristics model. We found that an unstable point in a MOBILE affects its operation, and false operation occurs when the amplitude of the clock signal is inappropriate. From a calculation of transient time using peak-to-valley current ratio (PVR) and peak current density (jP) as parameters, we also discovered that a sufficiently high jP and higher PVR (>6) are necessary for high-speed operations. View full abstract»

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  • Hot-carrier degradation phenomena in lateral and vertical DMOS transistors

    Page(s): 623 - 628
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    The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Upon hot-carrier stress, two different, and competing degradation mechanisms are present: channel electron mobility reduction due to interface trap formation, and injection and trapping of hot holes in the accumulation region of the transistor. It will be shown that the latter mechanism is absent in the vertical DMOS. View full abstract»

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  • Turn-off switching analysis considering dynamic avalanche effect for low turn-off loss high-voltage IGBTs

    Page(s): 629 - 635
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    An avalanche generation phenomenon has a large influence on turn-off switching loss and reverse-biased safe operating area of high-voltage insulated gate bipolar transistors (IGBTs). The purpose of this paper is to clarify the correlation between the avalanche multiplication phenomenon and the turn-off characteristics. We introduce a turn-off switching analytical model of IGBTs that considers the avalanche multiplication effect. It is concluded that the criterion of dynamic avalanche depends on the gate resistance. In the case of 4.5-kV IGBTs, the gate resistance of more than 200 Ω·cm2 is needed to suppress the dynamic avalanche generation under a clumped inductive load circuit. On the contrary, the turn-off switching loss increases in the case that the gate resistance RG is increased to more than approximately 100 Ω·cm2. Theses results show that to realize low turn-off switching loss, it is necessary to ensure that the gate resistance is below a constant value, such as 100 Ω·cm2. However, at high current density, such as 80 A/cm2, the dynamic avalanche will generate under such small gate resistance condition. Therefore, it is important to develop IGBTs without destruction even under the condition of dynamic avalanche generation. View full abstract»

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  • 4.5-kV injection-enhanced gate transistors (IEGTs) with high turn-off ruggedness

    Page(s): 636 - 641
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    Although high blocking voltage insulated gate bipolar transistors (IGBTs) have wider safe operating areas (SOAs) than do gate turn-off thyristors, a failure problem remains at turn-off transient. The purpose of this paper is to clarify the mechanism of failure at turn-off transient and to develop a high-voltage injection-enhanced gate transistors (IEGTs) with wide SOA at turn-off transient [wide reverse-biased SOA (RBSOA)]. We discuss this destruction mechanism in detail on the basis of comparison of experimental results with calculated results obtained by an analytical model considering dynamic avalanche generation. These results lead to the conclusion that the design of the n-emitter and the control of avalanche generation onset are key parameters for realizing high ruggedness of high-voltage IEGT. Based on the proper design of the n-emitter and the gate driving condition, a high-voltage and high-current 4.5-kV IEGT with wide RBSOA, keeping low saturation voltage and low turn-off switching loss, has been successfully developed. View full abstract»

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  • Efficient improvement of hot carrier-induced degradation for 0.1-μm indium-halo nMOSFET

    Page(s): 642 - 644
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    The effect of post-thermal annealing after indium-halo implantation on the reliability of sub-0.1-μm nMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot carrier-induced device degradation. The best results of device performance were obtained with post-annealing treatment performed at medium temperatures (e.g., 900°C) for a longer time. View full abstract»

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  • Rate equation of current degradation of the Spindt-type field emitter array

    Page(s): 644 - 646
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    The degradation rate of the emission current of the Spindt-type field emitter arrays in the display environment has been measured. The relative degradation rate is found to be a function of the square of emission current and proportional to the anode bias (voltage). A life model is presented that leads to development of an analytical rate equation of emission current degradation. Based on this model, there is a steady-state level at which the emission current is stable. The steady-state emission current depends on anode bias, background pressure in the package and cleanliness of anode and cathode surfaces. Experimental results are consistent with the rate equation derived from the model. Since the model does not include any material and process that make the cathode, it could probably apply to any field emission cathodes. View full abstract»

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  • A simple method to extract intrinsic and extrinsic base-collector capacitances of bipolar transistors

    Page(s): 647 - 650
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    A new and direct method is proposed to determine intrinsic (Cμ) and extrinsic (Cμx) base-collector junction capacitances of bipolar junction transistors (BJTs). The voltage dependent curves of Cμ and Cμx are obtained by using a new Y-parameter equation that is derived from a simplified "cut-off mode" equivalent circuit including ac current crowding capacitance. This new method is superior to several conventional ones, because it remains valid when there is ac emitter current crowding. The superiority of the new method has been verified by observing much better agreement of modeled gain with measured ones than the conventional method. View full abstract»

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  • IEEE 2004 International Integrated Reliability Workshop

    Page(s): 651
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    Freely Available from IEEE
  • IEEE International Semiconductor Conference

    Page(s): 652
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    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology