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Computers, IEEE Transactions on

Issue 5 • Date May 2004

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Displaying Results 1 - 13 of 13
  • Efficient and accurate analytical modeling of whole-program data cache behavior

    Publication Year: 2004 , Page(s): 547 - 566
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (923 KB) |  | HTML iconHTML  

    Data caches are a key hardware means to bridge the gap between processor and memory speeds, but only for programs that exhibit sufficient data locality in their memory accesses. Thus, a method for evaluating cache performance is required to both determine quantitatively cache misses and to guide data cache optimizations. Existing analytical models for data cache optimizations target mainly isolate... View full abstract»

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  • Power-aware scheduling for periodic real-time tasks

    Publication Year: 2004 , Page(s): 584 - 600
    Cited by:  Papers (160)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1486 KB) |  | HTML iconHTML  

    We address power-aware scheduling of periodic tasks to reduce CPU energy consumption in hard real-time systems through dynamic voltage scaling. Our intertask voltage scheduling solution includes three components: 1) a static (offline) solution to compute the optimal speed, assuming worst-case workload for each arrival, 2) an online speed reduction mechanism to reclaim energy by adapting to the act... View full abstract»

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  • Experiences, strategies, and challenges in building fault-tolerant CORBA systems

    Publication Year: 2004 , Page(s): 497 - 511
    Cited by:  Papers (28)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (828 KB) |  | HTML iconHTML  

    It has been almost a decade since the earliest reliable CORBA implementation and, despite the adoption of the fault-tolerant CORBA (FT-CORBA) standard by the Object Management Group, CORBA is still not considered the preferred platform for building dependable distributed applications. Among the obstacles to FT-CORBA's widespread deployment are the complexity of the new standard, the lack of unders... View full abstract»

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  • A performance model for wormhole-switched interconnection networks under self-similar traffic

    Publication Year: 2004 , Page(s): 601 - 613
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (907 KB) |  | HTML iconHTML  

    Many recent studies have convincingly demonstrated that network traffic exhibits a noticeable self-similar nature, which has a considerable impact on queuing performance. However, the networks used in current multicomputers have been primarily designed and analyzed under the assumption of the traditional Poisson arrival process, which is inherently unable to capture traffic self-similarity. Conseq... View full abstract»

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  • EPIC: profiling the propagation and effect of data errors in software

    Publication Year: 2004 , Page(s): 512 - 530
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1630 KB) |  | HTML iconHTML  

    We present an approach for analyzing the propagation and effect of data errors in modular software enabling the profiling of the vulnerabilities of software to find 1) the modules and signals most likely exposed to propagating errors and 2) the modules and signals which, when subjected to error, tend to cause more damage than others from a systems operation point-of-view. We discuss how to use the... View full abstract»

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  • Implications of clock distribution faults and issues with screening them during manufacturing testing

    Publication Year: 2004 , Page(s): 531 - 546
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2437 KB) |  | HTML iconHTML  

    Based on real process data of a reference microprocessor, fault models are derived for the manufacturing defects most likely to affect signals of the clock distribution network. Their probability is estimated with Inductive Fault Analysis performed on the actual layout of the reference microprocessor. The effects of the most likely faults have been evaluated by electrical level simulations. We hav... View full abstract»

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  • Deriving deadlines and periods for real-time update transactions

    Publication Year: 2004 , Page(s): 567 - 583
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (624 KB) |  | HTML iconHTML  

    Typically, temporal validity of real-time data is maintained by periodic update transactions. We examine the problem of period and deadline assignment for these update transactions such that 1) these transactions can be guaranteed to complete by their deadlines and 2) the imposed CPU workload is minimized. To this end, we propose a novel approach, named the More-Less approach. By applying this app... View full abstract»

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  • Design verification by test vectors and arithmetic transform universal test set

    Publication Year: 2004 , Page(s): 628 - 640
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1048 KB) |  | HTML iconHTML  

    We investigate methodology for simulation-based verification under a fault model. Since it is currently not feasible to describe a comprehensive explicit model of design errors, we propose an implicit fault model. The model is based on the arithmetic transform (AT) spectral representation of faults. The verification of circuits under the small errors in spectral domain is then performed by the uni... View full abstract»

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  • A method enabling feasible conformance test sequence generation for EFSM models

    Publication Year: 2004 , Page(s): 614 - 627
    Cited by:  Papers (41)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1171 KB) |  | HTML iconHTML  

    A formal description of an implementation under test (IUT), such as its VHDL behavior description, is required to automatically generate feasible test sequences for the IUT. Although finite-state machines (FSMs) can be used to describe the control structures of communication protocols, the data portion can only be modeled by extended finite-state machines (EFSMs). However, infeasible paths due to ... View full abstract»

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  • IEEE Trans. on Computers - Table of Content

    Publication Year: 2004 , Page(s): 0_1
    Save to Project icon | Request Permissions | PDF file iconPDF (275 KB)  
    Freely Available from IEEE
  • IEEE Computer Society's - Staff List

    Publication Year: 2004 , Page(s): 0_2
    Save to Project icon | Request Permissions | PDF file iconPDF (206 KB)  
    Freely Available from IEEE
  • TC: Information for authors

    Publication Year: 2004 , Page(s): 641
    Save to Project icon | Request Permissions | PDF file iconPDF (206 KB)  
    Freely Available from IEEE
  • IEEE Computer Society Information

    Publication Year: 2004 , Page(s): 642
    Save to Project icon | Request Permissions | PDF file iconPDF (275 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org