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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 7 • Date Jul 1991

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Displaying Results 1 - 11 of 11
  • Fast batch incremental netlist compilation hierarchical schematics

    Publication Year: 1991, Page(s):922 - 931
    Cited by:  Papers (4)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    Fast batch and incremental algorithms for creating and updating the netlist underlying a hierarchical schematic design are presented. The algorithms can be used either for maintaining the netlist as a data structure for further online processing or as a file for use with other offline design tools that are downstream from the compilation process. The batch algorithm uses a preorder traversal of th... View full abstract»

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  • Minimum area layout of series-parallel transistor networks is NP-hard

    Publication Year: 1991, Page(s):943 - 949
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    Functional cells are a physical realization of complex MOS gates. Efficient algorithms for minimizing the width of a functional cell are known. Every solution to the width minimization problem leads to a cell of a certain height. It is shown that, even for functional cells of complex MOS gates represented by series-parallel transistor networks, the problem of finding a solution of minimum width th... View full abstract»

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  • Piecewise approximate circuit simulation

    Publication Year: 1991, Page(s):861 - 870
    Cited by:  Papers (52)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB)

    A simulation methodology for the nonlinear transient analysis of electrical circuits is described. Equations are formulated on the tree/link basis. All branch and node variables are modeling to be piecewise approximate in time. Electronic devices are represented by empirical table models of I-V characteristics. The table models may be built at various levels of precision, and con... View full abstract»

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  • The ADAM design planning engine

    Publication Year: 1991, Page(s):829 - 846
    Cited by:  Papers (19)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1712 KB)

    A novel paradigm for managing the digital process is presented. Under this paradigm, design is seen as a process in which abstract models of design tools are applied to abstract models of design states in a simulated or planning space, until a sequence of design tasks has been constructed to completion. Important parameters of the hypothetical design represented by the terminal states are then est... View full abstract»

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  • Ratio cut partitioning for hierarchical designs

    Publication Year: 1991, Page(s):911 - 921
    Cited by:  Papers (104)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (904 KB)

    Circuit partitioning for hierarchical VLSI design is addressed. A partitioning approach called ratio cut is proposed. It is demonstrated that the ratio cut algorithm can locate the clustering structures in the circuit. Finding the optimal ratio cut is NP-complete. However, in certain cases the ratio cut can be solved by linear programming techniques via the multicommodity flow formulation. Also pr... View full abstract»

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  • Easily testable gate-level and DCVS multipliers

    Publication Year: 1991, Page(s):932 - 942
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    Some C-testable designs of a carry-save parallel multiplier are presented. Results are given for both the gate-level implementation and the differential cascode voltage switch (DCVS) implementation. DCVS circuits are dynamic CMOS circuits which have the advantage of being protected against test set invalidation due to circuit delays. In the first gate-level design, it is assumed that the full-adde... View full abstract»

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  • Group delay as an estimate of delay in logic

    Publication Year: 1991, Page(s):949 - 953
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    It is an accepted practice in signal delay estimation to model MOS digital circuits as RC circuits. In most cases Elmore's definition is exactly equivalent to the group delay of the network at zero frequency. A computationally efficient noniterative method to calculate this delay for networks with any linear elements and arbitrary topology is presented. It is shown that in RC net... View full abstract»

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  • Massively parallel switch-level simulation: a feasibility study

    Publication Year: 1991, Page(s):871 - 894
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2368 KB)

    The feasibility of mapping the COSMOS switch-level simulator onto a computer with thousands of simple processors is addressed. COSMOS preprocesses transistor networks into Boolean behavioral models, capturing the switch-level behavior of a circuit in a set of Boolean formulas. A class of massively parallel computers and a mapping of COSMOS onto these computers are described. The factors affecting ... View full abstract»

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  • Architectural partitioning for system level synthesis of integrated circuits

    Publication Year: 1991, Page(s):847 - 860
    Cited by:  Papers (52)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1308 KB)

    APARTY is an architectural partitioning tool that uses a novel multistage clustering algorithm to extract the high level structure of an IC design by concentrating on area and interconnect considerations. Performance is addressed implicitly. APARTY works within the framework of the system architect's workbench and can pass system-level structural information along to register-transfer level (RTL) ... View full abstract»

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  • A new methodology for the design centering of IC fabrication processes

    Publication Year: 1991, Page(s):895 - 903
    Cited by:  Papers (33)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    The authors describe a practical methodology that can be applied to optimize the process yield of IC fabrication lines. The yield maximization problem is first reformulated into a deterministic design centering problem. Macromodeling and problem decomposition are then applied to solve the design centering problem efficiently. The effectiveness of this methodology is illustrate through a simulation... View full abstract»

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  • Simulation lossless symmetrical three conductor systems

    Publication Year: 1991, Page(s):904 - 910
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The treatment of symmetrical lossless three-conductor transmission lines with arbitrary terminations and umped coupling elements is reduced to a set of four delay elements and analog interface networks modeling the mode conversion in unsymmetrical terminations or coupling elements between the lines. The model can easily be programmed in circuit simulators like SPICE using the respective t... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu