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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 7 • Date Jul 1991

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Displaying Results 1 - 11 of 11
  • Minimum area layout of series-parallel transistor networks is NP-hard

    Page(s): 943 - 949
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    Functional cells are a physical realization of complex MOS gates. Efficient algorithms for minimizing the width of a functional cell are known. Every solution to the width minimization problem leads to a cell of a certain height. It is shown that, even for functional cells of complex MOS gates represented by series-parallel transistor networks, the problem of finding a solution of minimum width that also minimizes the height is NP-hard View full abstract»

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  • Group delay as an estimate of delay in logic

    Page(s): 949 - 953
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    It is an accepted practice in signal delay estimation to model MOS digital circuits as RC circuits. In most cases Elmore's definition is exactly equivalent to the group delay of the network at zero frequency. A computationally efficient noniterative method to calculate this delay for networks with any linear elements and arbitrary topology is presented. It is shown that in RC networks under certain conditions, the Elmore delay and the 50% unit step response delay are related by a constant which is largely independent of the element values and topology. An efficient method to obtain sensitivities of the delay with respect to any element in the network is presented View full abstract»

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  • Massively parallel switch-level simulation: a feasibility study

    Page(s): 871 - 894
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    The feasibility of mapping the COSMOS switch-level simulator onto a computer with thousands of simple processors is addressed. COSMOS preprocesses transistor networks into Boolean behavioral models, capturing the switch-level behavior of a circuit in a set of Boolean formulas. A class of massively parallel computers and a mapping of COSMOS onto these computers are described. The factors affecting the performance of such a massively parallel simulator are discussed, including: the amount of parallelism in the simulation model, performance measures for massively parallel machines, and the impact of event scheduling on simulator performance. Compilation tools that automatically map a MOS circuit onto a massively parallel computer have been developed. Techniques for restructuring Boolean expressions for greater parallelism and mapping Boolean expressions for evaluation on massively parallel machines are described. Massively parallel switch-level simulation is illustrated by a pilot implementation on a 32k-processor Thinking Machines Connection Machine system View full abstract»

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  • Fast batch incremental netlist compilation hierarchical schematics

    Page(s): 922 - 931
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    Fast batch and incremental algorithms for creating and updating the netlist underlying a hierarchical schematic design are presented. The algorithms can be used either for maintaining the netlist as a data structure for further online processing or as a file for use with other offline design tools that are downstream from the compilation process. The batch algorithm uses a preorder traversal of the design hierarchy to derive the netlist. The incremental algorithm trims this traversal to only those paths leading to changes in the netlist. For most user modifications the netlist can be incrementally updated in a fraction of the time required using batch compilation techniques, often with no perceivable delay to the user View full abstract»

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  • Simulation lossless symmetrical three conductor systems

    Page(s): 904 - 910
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    The treatment of symmetrical lossless three-conductor transmission lines with arbitrary terminations and umped coupling elements is reduced to a set of four delay elements and analog interface networks modeling the mode conversion in unsymmetrical terminations or coupling elements between the lines. The model can easily be programmed in circuit simulators like SPICE using the respective transmission line models in combination with the above-mentioned interface networks. Crosstalk between bus lines is discussed as an example View full abstract»

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  • Piecewise approximate circuit simulation

    Page(s): 861 - 870
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    A simulation methodology for the nonlinear transient analysis of electrical circuits is described. Equations are formulated on the tree/link basis. All branch and node variables are modeling to be piecewise approximate in time. Electronic devices are represented by empirical table models of I-V characteristics. The table models may be built at various levels of precision, and concomitant accuracy levels are reflected in the simulation results. Simulation accuracy may be varied on a branch-by-branch basis or global basis, this permitting the user to distribute computer resources in a meaningful manner. The simulation algorithm is event driven and fully exploits temporal sparsity in the underlying circuit equations. Mechanisms for dealing with steady-state situations and stiff circuits have been investigated. A prototype simulator, SPECS, has been developed and tested on large industrial integrated circuits. It has proven to be a reliable and efficient tool in the analysis of digital and mixed circuits View full abstract»

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  • Architectural partitioning for system level synthesis of integrated circuits

    Page(s): 847 - 860
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    APARTY is an architectural partitioning tool that uses a novel multistage clustering algorithm to extract the high level structure of an IC design by concentrating on area and interconnect considerations. Performance is addressed implicitly. APARTY works within the framework of the system architect's workbench and can pass system-level structural information along to register-transfer level (RTL) tools to guide the completion of a data-path design. The multistage clustering algorithm and how it is used by APARTY to choose partitions are described. The system architect's workbench and how architectural partitioning can be used to guide synthesis are also described. Results of using APARTY in the design process show improved register-transfer designs. In particular, the number of global routing wires is generally reduced by over 50% by following the partitioning scheme suggested by APARTY View full abstract»

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  • A new methodology for the design centering of IC fabrication processes

    Page(s): 895 - 903
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    The authors describe a practical methodology that can be applied to optimize the process yield of IC fabrication lines. The yield maximization problem is first reformulated into a deterministic design centering problem. Macromodeling and problem decomposition are then applied to solve the design centering problem efficiently. The effectiveness of this methodology is illustrate through a simulation example involving a CMOS process adopted from an industrial line View full abstract»

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  • Easily testable gate-level and DCVS multipliers

    Page(s): 932 - 942
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    Some C-testable designs of a carry-save parallel multiplier are presented. Results are given for both the gate-level implementation and the differential cascode voltage switch (DCVS) implementation. DCVS circuits are dynamic CMOS circuits which have the advantage of being protected against test set invalidation due to circuit delays. In the first gate-level design, it is assumed that the full-adders have any arbitrary, irredundant logic implementation. Such a design is C-testable with only nine test vectors, which detect all single stuck-at-faults. For a specific logic implementation of the full-adders, another design is shown to be C-testable with only six test vectors. The DCVS design is also C-testable with only six test vectors, which detect all detectable stuck-at, and stuck-open faults in the circuit. Both the hardware and delay overhead for all C-testable designs are very small. For three C-testable designs of the 32 by 32 multiplier, the hardware overhead is 2.7% or less and the delay overhead is 2.4% or less View full abstract»

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  • The ADAM design planning engine

    Page(s): 829 - 846
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    A novel paradigm for managing the digital process is presented. Under this paradigm, design is seen as a process in which abstract models of design tools are applied to abstract models of design states in a simulated or planning space, until a sequence of design tasks has been constructed to completion. Important parameters of the hypothetical design represented by the terminal states are then estimated. Either the planning is then repeated, or the sequence, or plan, is then executed, or carried out, in an execution space. This execution is monitored for violation of expectations; if violations occur, control is returned to the planner. The knowledge base of the planner is populated with register-transfer level (RTL) concepts for digital system design; it can also be populated with other knowledge sets. The planner forms part of the USC advanced design automation (ADAM) system View full abstract»

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  • Ratio cut partitioning for hierarchical designs

    Page(s): 911 - 921
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    Circuit partitioning for hierarchical VLSI design is addressed. A partitioning approach called ratio cut is proposed. It is demonstrated that the ratio cut algorithm can locate the clustering structures in the circuit. Finding the optimal ratio cut is NP-complete. However, in certain cases the ratio cut can be solved by linear programming techniques via the multicommodity flow formulation. Also proposed is a fast heuristic algorithm running in linear time with respect to the number of pins in the circuit. Experiments show good results in all tested cases View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu