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IEE Proceedings - Computers and Digital Techniques

Issue 2 • 19 March 2004

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Displaying Results 1 - 8 of 8
  • Energy-delay efficient filter cache hierarchy using pattern prediction scheme

    Publication Year: 2004, Page(s):141 - 146
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (730 KB)

    Filter cache (FC) is an auxiliary cache much smaller than the main cache. The FC is closest in hierarchy to the instruction fetch unit and it must be small in size to achieve energy-efficient realisations. A pattern prediction scheme is adapted to maximise energy savings in the FC hierarchy. The pattern prediction mechanism proposed relies on the spatial hit or miss pattern of the instruction acce... View full abstract»

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  • Algorithm and architecture for a high density, low power scalar product macrocell

    Publication Year: 2004, Page(s):161 - 172
    Cited by:  Papers (3)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (927 KB)

    The authors present a design approach for an arithmetic macrocell that computes the scalar product of two vectors, an operation ubiquitously present in the solution of many communications and digital signal processing problems. The core of the proposed architecture is a full combinational design containing a partial product generator, a partial product accumulator and a vector accumulator. The des... View full abstract»

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  • LANG - algorithm for constructing unique input/output sequences in finite-state machines

    Publication Year: 2004, Page(s):131 - 140
    Cited by:  Papers (2)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (325 KB)

    Finite-state-machines (FSMs) model a variety of hardware and software systems. Unique input/output (UIO) sequences are used in generation of test sequences to verify that a machine is in an expected state, which in turn ensures system reliability. The paper presents an efficient algorithm for computing UIO sequences for completely and incompletely specified FSMs with binary inputs. Set of states w... View full abstract»

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  • Modelling economics of DFT and DFY: a profit perspective

    Publication Year: 2004, Page(s):119 - 126
    Cited by:  Papers (3)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (392 KB)

    Because of the rapid increase in the complexity of VLSI circuits, a yield of 100% is virtually impossible. The problem rises intuitively: how can design for testability (DFT) and design for yield (DFY) be combined so as to save money? This question must be dealt with today for SOC designs at an early stage of the design cycle. To address this problem, a profit-evaluation system (PES) for IC design... View full abstract»

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  • Multiplier architectures for GF(p) and GF(2n)

    Publication Year: 2004, Page(s):147 - 160
    Cited by:  Papers (16)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (729 KB)

    Two new hardware architectures are proposed for performing multiplication in GF(p) and GF (2n), which are the most time-consuming operations in many cryptographic applications. The architectures provide very fast and efficient execution of multiplication in both GF(p) and GF(2n), and can be mainly used in elliptic curve cryptography. Both architectures are scalable and theref... View full abstract»

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  • Simulation study of memory performance of SMP multiprocessors running a TPC-W workload

    Publication Year: 2004, Page(s):93 - 109
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1698 KB)

    The infrastructure to support electronic commerce is one of the areas where more processing power is needed. A multiprocessor system can offer advantages for running electronic commerce applications. The memory performance of an electronic commerce server, i.e. a system running electronic commerce applications, is evaluated in the case of shared-bus multiprocessor architecture. The software archit... View full abstract»

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  • Residue-to-binary decoder for an enhanced moduli set

    Publication Year: 2004, Page(s):127 - 130
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (221 KB)

    Previous publications have given the moduli set (2n, 2n-1, 2n+1) considerable attention. In the residue number system literature this moduli set was referred to as the popular set. However, the dynamic range of this set is limited to 3n bits. A new moduli set (22n, 2n-1, 2n+1) is proposed with a dynamic range of 4n bits. This enhanc... View full abstract»

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  • Freshness specification for a class of asynchronous communication mechanisms

    Publication Year: 2004, Page(s):110 - 118
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (728 KB)

    The paper is concerned with a common form of asynchronous communication mechanism (ACM) which can be used to connect a single writer to a single reader, so that the intermediate data in the ACM can be updated at any time by the writer and can be inspected at any time by the reader, without recourse to arbitration or exclusion which would impede either writer or reader. A class of such ACMs is cons... View full abstract»

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Aims & Scope

Published from 1994-2006, IEE Proceedings - Computers and Digital Techniques contained significant and original contributions on computers, computing and digital techniques. It contained technical papers describing research and development work in all aspects of digital system-on-chip design and the testing of electronic and embedded systems, including the development of design automation tools. It was aimed at researchers, engineers and educators in the fields of computer and digital systems design and testing.

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