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Micro, IEEE

Issue 3 • Date June 1991

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Displaying Results 1 - 5 of 5
  • The Metaflow architecture

    Publication Year: 1991 , Page(s): 10 - 13
    Cited by:  Papers (16)  |  Patents (218)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1403 KB)  

    The Metaflow architecture, a unified approach to maximizing the performance of superscalar microprocessors, is introduced. The Metaflow architecture exploits inherent instruction-level parallelism in conventional sequential programs by hardware means, without relying on optimizing compilers. It is based on a unified structure, the DRIS (deferred-scheduling, register-renaming instruction shelf), that manages out-of-order execution and most of the attendant problems. Coupling the DRIS with a speculative-execution mechanism that avoids conditional branch stalls results in performance limited only be inherent instruction-level parallelism and available execution resources. Although presented in the context of superscalar machines, the technique is equally applicable to a superpipelined implementation. Lightning, the first implementation of the Metaflow architecture, which executes the Sparc RISC instruction set is described.<> View full abstract»

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  • IBM RISC System/6000: architecture and performance

    Publication Year: 1991 , Page(s): 14 - 17
    Cited by:  Papers (8)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1444 KB)  

    The IBM RISC System/6000, a superscalar microprocessor, is presented. The architecture of this processor has its instruction set specifically designed for a superscalar machine containing three independent units-branch, fixed-point, and floating-point. The design also emphasizes high-performance floating-point operations. The design principles are to offer maximum overlap of the three functional units, avoid dead cycles, and define instructions that can (for the most part) be completed at a rate of one per cycle. The branch cycle, fixed- and floating-point units, cache management, and performance are described. Benchmark results are given.<> View full abstract»

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  • Design and implementation trade-offs in the Clipper C400 architecture

    Publication Year: 1991 , Page(s): 18 - 21
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1500 KB)  

    A description is given of the C400, the first complete redesign of the Clipper reduced instruction-set computing architecture since its introduction in 1985. The C400 delivers three times the performance of the C300, yet retains full-code compatibility with earlier Clippers. The C400 combines two architectural approaches to attain its performance goals. The first approach, superscalar operation, allows the processor to begin the execution of more than one instruction during each clock cycle. The C400, which is moderately superscalar, can dispatch two instructions per clock cycle. The C400 also embodies the design concept of superpipelining, an approach that emphasizes high clock rates and deep execution pipelines in attaining high computational performance. The discussion covers the programming model, early hardware implementations, the C400 project goals and approaches, C400 performance, the integer unit design, the load/store pipeline, the floating-point unit design, the superscalar/superpipelined architecture, circuit design, and the advantages of the multichip implementation.<> View full abstract»

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  • Datawave: a single-chip multiprocessor for video applications

    Publication Year: 1991 , Page(s): 22 - 25
    Cited by:  Papers (5)  |  Patents (77)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1430 KB)  

    A fine-grained MIMD (multiple-instruction, multiple-data) array processor for video applications that combines submicron technology, parallel processing, and dataflow programming is presented. The Datawave processor is used as the building block of this cellular, data-driven system architecture. The processor executes statically scheduled dataflow programs, and self-timed hardware mechanisms handle the asynchronous dataflows automatically and transparently. The architecture is discussed first at the array level and then at the cell level. It is shown how Datawave implements a four-tap finite impulse response filer and a real-time image codec. Program development tools for Datawave are discussed, and the chip itself is briefly described.<> View full abstract»

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  • iWarp: a 100-MOPS, LIW microprocessor for multicomputers

    Publication Year: 1991 , Page(s): 26 - 29
    Cited by:  Papers (28)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1310 KB)  

    An architecture that efficiently supports both message-passing and systolic communications in one system is presented. This architecture incorporates a variety of innovative features unifying both computational power and communications flexibility in one VLSI component, the iWarp microprocessor. The message-based communication model is discussed, and an overview of the architecture is given. Two principle iWarp components, called the communication agent and the computation agent, and the register file they share are described. The efficiencies of word-level communication are examined. The software development environment is also described.<> View full abstract»

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