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IEEE Micro

Issue 3 • June 1991

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Displaying Results 1 - 5 of 5
  • The Metaflow architecture

    Publication Year: 1991, Page(s):10 - 13
    Cited by:  Papers (19)  |  Patents (225)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1403 KB)

    The Metaflow architecture, a unified approach to maximizing the performance of superscalar microprocessors, is introduced. The Metaflow architecture exploits inherent instruction-level parallelism in conventional sequential programs by hardware means, without relying on optimizing compilers. It is based on a unified structure, the DRIS (deferred-scheduling, register-renaming instruction shelf), th... View full abstract»

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  • IBM RISC System/6000: architecture and performance

    Publication Year: 1991, Page(s):14 - 17
    Cited by:  Papers (10)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1444 KB)

    The IBM RISC System/6000, a superscalar microprocessor, is presented. The architecture of this processor has its instruction set specifically designed for a superscalar machine containing three independent units-branch, fixed-point, and floating-point. The design also emphasizes high-performance floating-point operations. The design principles are to offer maximum overlap of the three functional u... View full abstract»

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  • Design and implementation trade-offs in the Clipper C400 architecture

    Publication Year: 1991, Page(s):18 - 21
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1500 KB)

    A description is given of the C400, the first complete redesign of the Clipper reduced instruction-set computing architecture since its introduction in 1985. The C400 delivers three times the performance of the C300, yet retains full-code compatibility with earlier Clippers. The C400 combines two architectural approaches to attain its performance goals. The first approach, superscalar operation, a... View full abstract»

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  • Datawave: a single-chip multiprocessor for video applications

    Publication Year: 1991, Page(s):22 - 25
    Cited by:  Papers (8)  |  Patents (99)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1430 KB)

    A fine-grained MIMD (multiple-instruction, multiple-data) array processor for video applications that combines submicron technology, parallel processing, and dataflow programming is presented. The Datawave processor is used as the building block of this cellular, data-driven system architecture. The processor executes statically scheduled dataflow programs, and self-timed hardware mechanisms handl... View full abstract»

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  • iWarp: a 100-MOPS, LIW microprocessor for multicomputers

    Publication Year: 1991, Page(s):26 - 29
    Cited by:  Papers (85)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1310 KB)

    An architecture that efficiently supports both message-passing and systolic communications in one system is presented. This architecture incorporates a variety of innovative features unifying both computational power and communications flexibility in one VLSI component, the iWarp microprocessor. The message-based communication model is discussed, and an overview of the architecture is given. Two p... View full abstract»

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Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center