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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • September 1987

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Displaying Results 1 - 20 of 20
  • Editorial

    Publication Year: 1987, Page(s): 693
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  • On Delay Fault Testing in Logic Circuits

    Publication Year: 1987, Page(s):694 - 703
    Cited by:  Papers (360)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1616 KB)

    Correct operation of a logic circuit requires propagation delays of all paths in the circuit to be smaller than the intended "clock interval." Random or deterministic tests, conducted at the normal clocking rate, can be used to insure that path delays in manufactured circuits meet the specifications. Algorithms, based on a five-valued logic system, to accurately calculate the detection probability... View full abstract»

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  • Accelerated Fault Simulation and Fault Grading in Combinational Circuits

    Publication Year: 1987, Page(s):704 - 712
    Cited by:  Papers (92)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1360 KB)

    The principles of fault simulation and fault grading are introduced by a general description of the problem. Based upon the well-known concept of restricting fault simulation to the fanout stems and of combining it with a backward traversal inside the fanout-free regions of the circuit, proposals are presented to further accelerate fault simulation and fault grading. These proposals aim at paralle... View full abstract»

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  • On the C-Testability of Generalized Counters

    Publication Year: 1987, Page(s):713 - 726
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2072 KB)

    This paper investigates the testability of a class of circuits, called counters, that perform the addition of sets of input bits of equal arithmetic weight. These circuits consist of full and half adders interconnected in an iterative manner defined by the counting process. The general class of counter circuits contain reconvergent fanouts and are not as structurally regular as one- or two-dimensi... View full abstract»

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  • Multiple-Valued Minimization for PLA Optimization

    Publication Year: 1987, Page(s):727 - 750
    Cited by:  Papers (198)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4016 KB)

    This paper describes both a heuristic algorithm, Espresso-MV, and an exact algorithm, Espresso-EXACT, for minimization of multiple-valued input, binary-valued output logic functions. Minimization of these functions is an important step in the optimization of programmable logic arrays (PLA's). In particular, the problems of two-level multiple-output minimization, minimization of PLA's with input de... View full abstract»

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  • Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits

    Publication Year: 1987, Page(s):751 - 765
    Cited by:  Papers (35)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2688 KB)

    The quality of the design of large-scale integrated circuits is determined by such figures of merit as silicon area, power consumption, and switching-time performance. We address here the problem of the automatic synthesis of digital circuits with the goal of achieving high-performance designs. We assume we are given an intermediate circuit representation that optimizes area and/or power. We use t... View full abstract»

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  • Fast Methods for Switch-Level Verification of MOS Circuits

    Publication Year: 1987, Page(s):766 - 779
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2336 KB)

    Simulation of hardware is a commonly-used method for demonstrating that a circuit design will work for a restricted set of inputs. Verification is a method of proving a circuit design will work for all combinations of input values. Switch-level verification works directly from the circuit netlist. The performance of existing switch-level verifiers has been improved through a combination of techniq... View full abstract»

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  • A Scanline Data Structure Processor for VLSI Geometry Checking

    Publication Year: 1987, Page(s):780 - 794
    Cited by:  Papers (7)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2672 KB)

    This paper proposes an architecture to support VLSI geometry checking tasks based on scanline algorithms. Rather than recast the entire verification task in hardware, we identify primitives around which geometry checking tools can be built, and examine the feasibility of accelerating two of these critical primitives. We focus on the operations of Boolean combinations of mask layers, and region num... View full abstract»

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  • Optimal Chaining of CMOS Transistors in a Functional Cell

    Publication Year: 1987, Page(s):795 - 801
    Cited by:  Papers (83)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1312 KB)

    We describe an algorithm that maps a CMOS circuit diagram into an area-efficient, high-performance layout in the style of a transistor chain. It is superior to other published algorithms of this kind in terms of the class of input circuits it accepts, its efficiency, and the quality of the results it produces. This algorithm is intended for the automatic generation of basic cells in a custom or se... View full abstract»

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  • An Efficient Approach to Gate Matrix Layout

    Publication Year: 1987, Page(s):802 - 809
    Cited by:  Papers (42)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1176 KB)

    This paper proposes a new representation of nets for gate matrix layout, called dynamic-net-lists. The dynamic-net-list representation is better suited for layout optimization than the traditional fixed-net-list since with it net-bindings can be delayed until the gate-ordering has been constructed. Based on dynamic-net-lists, an efficient modified min-net-cut algorithm has been developed to solve ... View full abstract»

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  • Hierarchical Loose Routing for Gate Arrays

    Publication Year: 1987, Page(s):810 - 819
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1496 KB)

    In this paper, we present a new, quasi-parallel approach to the loose routing problem for gate array LSI design. It is based on a new modeling for the decomposition problem of each net using a compact net graph which maps sets of feed-throughs instead of individual ones. The loose routing is done by calculation of a minimum spanning tree in this net graph and by a proper embedding of the tree as a... View full abstract»

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  • Asymptotically Perfect Trivial Global Routing: A Stochastic Analysis

    Publication Year: 1987, Page(s):820 - 827
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1232 KB)

    A two-dimensional stochastic model of the global wiring of a VLSI chip in a standard-cell or sea-of-gates design style is defined; prominent in the model is the property that the probability of connecting two pins is solely a function of the distance between the cells containing them. It is also assumed that each net consists of just two pins. A lower bound is placed on the expected size of the ch... View full abstract»

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  • Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout

    Publication Year: 1987, Page(s):828 - 837
    Cited by:  Papers (79)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1528 KB)

    A new methodology for hierarchical floor planning and global routing for building block layout is presented. Unlike the traditional approach, which separates placement and global routing into two consecutive stages, our approach accomplishes both jobs simultaneously in a hierarchical fashion. The global routing problem is formulated at each level as a series of the minimum Steiner tree problem in ... View full abstract»

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  • A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells

    Publication Year: 1987, Page(s):838 - 847
    Cited by:  Papers (90)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1664 KB)

    A modification of the classical Simulated Annealing algorithm for the macro-cell placement problem is proposed for implementation on multiprocessor systems. The algorithm has been implemented on the Sequent Balance 8000, a multiprocessor system with a shared-memory architecture. Experimental results show that the new algorithm obtains results comparable in quality to those of the single processor ... View full abstract»

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  • Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations

    Publication Year: 1987, Page(s):848 - 862
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2456 KB)

    This paper presents the technique of concurrent hierarchical fault simulation, a performance model, and two hierarchical optimization techniques to enhance fault simulator performance. The mechanisms for these enhancements are demonstrated with a performance model and are validated experimentally via CHIEFS, the Concurrent Hierarchical and Extensible Fault Simulator, and WRAP, an offline hierarchy... View full abstract»

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  • Algorithmic Aspects of One-Dimensional Layout Compaction

    Publication Year: 1987, Page(s):863 - 878
    Cited by:  Papers (26)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2624 KB)

    We present a theory of one-dimensional layout compaction that is based on the graph theoretic approach used in such compacters as reported in [5], [7], [11], and [26]. Compaction here consists of two steps. In the first stage, a directed graph is extracted from the layout. In the second stage, compaction is performed by solving a single-source shortest path problem on this graph. The paper present... View full abstract»

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  • Sensitivity Analysis for Device Design

    Publication Year: 1987, Page(s):879 - 885
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1126 KB)

    In this paper, we propose a sensitivity analysis technique for device design. By this method, we determine the linearized variations of the device terminal characteristics following some change either in the impurity distribution, or in device geometry, such as channel length and oxide thickness. This technique has been implemented in our general-purpose two-dimensional device-analysis program, an... View full abstract»

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  • Metal--Metal Matrix (M 3) for High-Speed MOS VLSI Layout

    Publication Year: 1987, Page(s):886 - 891
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB)

    This paper proposes a new layout method for high-speed VLSI circuits in single-poly and double-metal MOS technology. With emphasis on the speed performance, our Metal-Metal Matrix (M 3) layout method employs maximal use of metal interconnections while restricting delay-consuming polysilicon or polycide features only to form MOS transistor gates or to connect the same type of transistor ... View full abstract»

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  • Local Transformations via Cube Operations

    Publication Year: 1987, Page(s):892 - 902
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1600 KB)

    Wislan is a language for describing computer hardware at the gate and functional levels of abstraction. After converting a WISLAN description to a gate table data structure, users interactively apply local transformations to that network to transform the gate network to a technology, meet technology limits, and optimize the network. A number of extensions to WISLAN and new, less-local transforms a... View full abstract»

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  • VLSI Layout Compaction with Grid and Mixed Constraints

    Publication Year: 1987, Page(s):903 - 910
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1344 KB)

    We investigate the modeling and solution techniques of VLSI layout compaction using the constraint graph approach under various practical design considerations. In particular, we extend the graph method to the compaction of VLSI layout with mixed grid constraints in addition to the usual minimum- and maximum-type constraints. This is a mixed integer problem. We show that it can be solved by the se... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu