Issue 5 • Date September 1987
Filter Results
-
-
On Delay Fault Testing in Logic Circuits
|
PDF (1616 KB)
-
-
On the C-Testability of Generalized Counters
|
PDF (2072 KB)
-
Multiple-Valued Minimization for PLA Optimization
|
PDF (4016 KB)
-
-
-
-
-
An Efficient Approach to Gate Matrix Layout
|
PDF (1176 KB)
-
Hierarchical Loose Routing for Gate Arrays
|
PDF (1496 KB)
-
-
Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout
|
PDF (1528 KB)
-
-
-
-
Sensitivity Analysis for Device Design
|
PDF (1128 KB)
-
-
Local Transformations via Cube Operations
|
PDF (1600 KB)
-
Aims & Scope
Contains articles on methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities.
Meet Our Editors
Editor-in-Chief
Sachin Sapatnekar
University of Minnesota
Dept. of Electrical and Computer Engineering
4-174 Keller Hall, 200 Union Street SE
Minneapolis, MN 55455 55455 USA
sachin@umn.edu


