IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • July 1987

Filter Results

Displaying Results 1 - 17 of 17
  • A Mixed HVH-VHV Algorithm for Three-Layer Channel Routing

    Publication Year: 1987, Page(s):497 - 502
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (840 KB)

    We present a hybrid three-layer channel-routing algorithm that combines horizontal-vertical-horizontal (HVH) and vertical-horizontal-vertical (VHV) approaches [1]. The result is the best of both approaches. VHV excels when the vertical constraint graph (VCG) has long chains; HVH is strong when the VCG has a large number of incomparable nodes. In hybrid routing, the VCG is partitioned into two port... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Channel-Routing Problem in the Knock-Knee Mode Is NP-Complete

    Publication Year: 1987, Page(s):503 - 506
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (568 KB)

    We will show that it is NP-Complete to decide whether an arbitrary instance of the channel-routing problem in the knock-knee mode can be laid out optimally. This result is extended to problems (arising in practice) involving nets of bounded degree View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Tile-Expansion Router

    Publication Year: 1987, Page(s):507 - 517
    Cited by:  Papers (38)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1588 KB)

    A router based on a tile-expansion algorithm and corner stitching data structure is presented. This program finds connections with a minimum number of jogs and it ensures that a possible solution will be found. Using a working tree, it allows an exhaustive and recursive search along all available areas for routing. The connections are made going back through the working tree until the starting ter... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Hierarchical Global Wiring Algorithm for Custom Chip Design

    Publication Year: 1987, Page(s):518 - 533
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2224 KB)

    We present a global wiring algorithm used in a top-down physical design environment, i.e., macros are laid out after global wiring is done, and wires are allowed to pass through macros (the wiring-through model). The floorplan of the chip is in the form of a slicing structure. The algorithm is based on a hierarchical scheme. The final result is obtained through a series of refinement as the proble... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Placement by Simulated Annealing on a Multiprocessor

    Publication Year: 1987, Page(s):534 - 549
    Cited by:  Papers (69)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2736 KB)

    Physical design tools based on simulated annealing algorithms have been shown to produce results of extremely high quality, but typically at a very high cost in execution time. This paper selects a representative annealing application--standard cell placement--and develops multiprocessor-based annealing algorithms for placement. A taxonomy of possible multiprocessor decompositions of annealing alg... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pad Assignment for Power Nets in VLSI Circuits

    Publication Year: 1987, Page(s):550 - 560
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1360 KB)

    This paper deals with the problem of single layer routing of power nets in building-block-style layout. It is assumed that power-supplying terminals are placed on the boundary of the chip and that each module within the chip has to be supplied by two or three different sources. The problem considered here is how to assign the power pads on the boundary of the chip so that their number is minimum w... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Formal Approach to Design-Rule Checking

    Publication Year: 1987, Page(s):561 - 573
    Cited by:  Papers (5)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1968 KB)

    This paper describes the development of a layout model and the theoretical basis for a relatively technology-independent, false-error free, hierarchical design-rule checker for VLSI circuit layouts which have Manhattan geometry and are subject to some design-rule simplifications. A flat model of the layout of a VLSI circuit using set theory notation is first defined. Two primitive operations and f... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Subthreshold Conduction Model for Circuit Simulation of Submicron MOSFET

    Publication Year: 1987, Page(s):574 - 581
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (840 KB)

    A circuit simulation model for subthreshold conduction of MOSFET is developed. This model employs a novel interpolation scheme to provide smooth transition from the subthreshold region to the above-threshold region. This interpolation scheme ensures that both channel current and its derivatives (or conductances) are smooth. Since an interpolation scheme is used, a simple, independent, and physical... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Inverse-Geometry Dependence of MOS Transistor Electrical Parameters

    Publication Year: 1987, Page(s):582 - 585
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (544 KB)

    Precise determination of transistor electrical parameters is essential for accurate circuit simulation. The strong geometric dependences of MOS transistor electrical parameters can be modeled by the inverse-geometry formula. However, special care is needed in using the inverse-geometry formula. To prevent the short-channel and narrow-width effects being adversely mirrored to the drain-current eval... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improved Simulation of p- and n-channel MOSFET's Using an Enhanced SPICE MOS3 Model

    Publication Year: 1987, Page(s):586 - 591
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (760 KB)

    Unrealistic parameter values and poor experimental agreement are two problems often encountered using the MOS3 model in SPICE2. The source of the discrepancy is attributed to MOS3's simplified treatment of the mobility degradation phenomenon, which generally results in an artifically exaggerated value for the carrier velocity. Practically, this discrepancy can be eliminated by introducing a new em... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis

    Publication Year: 1987, Page(s):592 - 600
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1448 KB)

    This paper presents a general methodology for designing optimal test structures and their applications to characterize the process fluctuations inherent in IC manufacturing. A set of test structures, including a novel test structure, is presented in which each test structure parameter is sensitive to a minimal number of process parameters. The procedure for device parameter extraction is described... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • HSS--A High-Speed Simulator

    Publication Year: 1987, Page(s):601 - 617
    Cited by:  Papers (79)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3024 KB)

    The High-Speed Simulator (HSS) is a fast and flexible system for gate-level fault simulation. Originally limited to combinational logic, it is being extended to handle sequential logic. It may also prove useful as a functional simulator. The speed of HSS is obtained by converting the cycle-free portions of a circuit into optimized machine code for a general-purpose computer. This compiled code sim... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Algorithmic Aspects of Symbolic Switch Network Analysis

    Publication Year: 1987, Page(s):618 - 633
    Cited by:  Papers (49)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2448 KB)

    A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean equations. For the class of networks that arise when analyzing digital metal-oxide semiconductor (MOS) ci... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Boolean Analysis of MOS Circuits

    Publication Year: 1987, Page(s):634 - 649
    Cited by:  Papers (121)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2616 KB)

    The switch-level model represents a digital metal-oxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically yields a set of Boolean formulas that describe the mapping from input and current state to the new n... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Timing Analysis and Performance Improvement of MOS VLSI Designs

    Publication Year: 1987, Page(s):650 - 665
    Cited by:  Papers (84)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2600 KB)

    TV is a MOS VLSI switch-level timing verifier. It has built-in direction-finding through pass transistors to minimize the number of false paths found, and has knowledge of clocking disciplines to increase the usefulness of timing analysis for chips with several clock phases. TV can find several distinct critical paths at once by using a modified breadth-first search, so that the number of runs of ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Distributed Approach to Timing Verification of Synchronous and Asynchronous Digital Designs

    Publication Year: 1987, Page(s):666 - 677
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1832 KB)

    A new approach to the timing verification of digital designs is introduced in this paper. The approach is capable of verifying synchronous and asynchronous digital designs including self-timed asynchronous circuits [10]. Every component in a circuit is represented by a timing description that may concurrently execute with other descriptions. Communication between and scheduling of the timing descr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Determining the Zeros and Poles of Linear Circuit Networks Using Function Approximation

    Publication Year: 1987, Page(s):678 - 690
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1688 KB)

    A numerical method for determining the significant singularities corresponding to the network function of a linear circuit is presented. This method is based upon function approximation of both the magnitude and phase of frequency response data. A linear network function of the form of a ratio of two polynomials in the Laplacian variable s is assumed. The frequency response data are approximated u... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu