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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 3 • Date May 1987

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Displaying Results 1 - 23 of 23
  • Foreword

    Publication Year: 1987 , Page(s): i - ii
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  • A Silicon Compiler System Based on Asynchronous Architecture

    Publication Year: 1987 , Page(s): 297 - 304
    Cited by:  Papers (1)
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    As one of the most promising approaches for the automatic generation of VLSI chips, the concept of "silicon compilers" was presented. A silicon compiler is a software system which accepts the behavioral or functional description of the chip and directly translates it to the layout patterns of the VLSI masks. In order to realize a design automation aid for full-custom VLSI chips for nonprofessional chip designers such as programmers, we have selected asynchronous architecture as the target model of the compiler and have been developing a silicon compiler system. A VLSI chip based on this architecture model consists of asynchronous modules which hold the control information internally. The behavior of the chip is controlled only by local communication among these modules. The silicon compiler system accepts the purely functional specifications of the chip, written by the hardware specification language ISPC, and directly translates it to the layout patterns in the form of CIF codes. By selecting an effective architecture model, it is possible to realize the silicon compiler system through simple translation programs which analyze the functional description of the chip and extract from it the configuration of components and the control information and through a library of the asynchronous modules which are generally defined with suitable parameters. View full abstract»

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  • High-Speed Logic Simulation on Vector Processors

    Publication Year: 1987 , Page(s): 305 - 321
    Cited by:  Papers (27)
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    In this paper, we propose logic simulation techniques using vector processors, or supercomputers with pipeline architecture, as a new approach to accelerating simulation speed. In order to use vector processors efficiently, we have to tune up the coding scheme or the basic algorithms to be suitable for vector processing. We developed three types of new simulation techniques for vector processing, which are dedicated for (1) zero-delay simulation of combinational circuits, (2) zero-delay simulation of synchronous sequential circuits, and (3) simulation with delay consideration. The first two are based on the compiler-driven method and the last on the event-driven method. We implemented logic simulators based on the above techniques on the FACOM VP-100 and VP-200 at Kyoto University and on the HITAC S-810/20 at the University of Tokyo. The maximum performance is about 7.7 x 10 9 gate-evaluations per second for combinational circuit simulation, 1.4 x 10 9 gate-evaluations per second for sequential circuit simulation (on the VP-200), and 230 x 10 3 events per second for timing simulation (on the S-810/20). These results are comparable to the performance of hardware simulation engines. Moreover, our techniques are so straightforward that we can implement them on most of the recent vector processors without serious modifications View full abstract»

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  • An Integrated Logic Design Environment Based on Behavioral Description

    Publication Year: 1987 , Page(s): 322 - 336
    Cited by:  Papers (20)  |  Patents (1)
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    This paper describes a new designer environment and its technical features for aiding in several design phases of digital equipment, including architecture, function, and logic design. The author and his coworkers have integrated an editor of a register transfer level (RTL) behavioral language, a translator, a simulator, and evaluation and optimization tools into a single system. In addition, they have developed a hardware synthesizer which automatically produces a gate-level connective description from the RTL behavioral description. With this new environment, designers can more quickly create designs and interactively change design data in the evaluation phase. Using this behavioral-description-based CAD environment, they designed a one-LSI-chip PROLOG machine with 33 independent control parts for executing unification and backtracking algorithms. The machine operates at 130 KLIPS, and is 18 213 gates in size. It took 7.8 person-months to carry out its architecture, function, and logic design. View full abstract»

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  • A Resistance Calculation Algorithm and Its Application to Circuit Extraction

    Publication Year: 1987 , Page(s): 337 - 345
    Cited by:  Papers (18)
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    This paper describes a resistance calculation program for a layout verification system called EMAP. A new resistance calculation algorithm, based on the finite-element method, and a generalized resistor model, used in this program, are discussed. Contact resistance effects, pinch resistors, and other kinds of resistance appearing in LSI's are considered in the proposed model. The proposed two-dimensional model, in which an inherent three-dimensional structure of resistors is embedded, allows efficient and accurate resistance calculation. The resistance value for an arbitrarily shaped multiregional resistivity and multiport resistor can be calculated efficiently by the proposed algorithm. The algorithm, called direct admittance matrix derivation, makes it possible to eliminate the tedious boundary condition treatment, and provides efficient matrix manipulation. Implementation techniques and related algorithms are discussed; these include resistor recognition from mask artwork, mesh generation for finite elements, node numbering for matrix bandwidth reduction, some properties of matrices appearing in the proposed algorithm, and a circuit representation method for the derived matrices. Some implementation results are also discussed. View full abstract»

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  • Symbolic Layout System: Application Results and Functional Improvements

    Publication Year: 1987 , Page(s): 346 - 354
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    This paper provides an outline, together with application results and functional improvements, of the symbolic layout system MGX. MGX was developed to support the layout design of the functional blocks of microprocessors for MOS technology. The point considered the most important when we started developing MGX is reducing design time without much waste of silicon area. In order to achieve this goal, a layout style in MGX in which all symbolic layout elements are on movable grid points and which has an orderly structure is adopted, and the fast compaction algorithm is selected. Another consideration for the system is to support the whole LSI layout process. Using MGX, a 16-bit microcontroller chip was successfully designed. MGX offered high transistor packing density and high productivity of the layout design. The experience with this layout design has shown that another goal to be achieved in the development of a symbolic layout system is the ability to update designed physical layout patterns with advances in LSI fabrication technology without having to redo the layout. Hence, MGX has been improved so as to deal with various design rules which may become possible with advances in LSI fabrication technology and to give higher transistor packing density. Experimental results show that the transistor packing density of the layout of a D flip-flop which is designed by using MGX increases by approximately 39 percent due to these improvements. View full abstract»

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  • Partitioning and Placement Technique for CMOS Gate Arrays

    Publication Year: 1987 , Page(s): 355 - 363
    Cited by:  Papers (10)  |  Patents (60)
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    This paper describes an automatic partitioning and placement system for CMOS gate arrays utilizing two different kinds of data: circuit structure and hierarchical design data. Characteristic circuit structures such as the bus structure and the iterative structure are automatically extracted and handled like single cells in the placement process. The partitioning process has employed two processes: one is the bottom-up extraction of these structures, and the other is the top-down process, which divides the given circuit into several subcircuits. Making use of the partitioning results, the placement program is also carried out by two-level processes: subcircuit-level placement and cell-level placement. Through experiments, it has been proved that the proposed technique is effective for attaining better layout results. View full abstract»

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  • A Practical CAD System Application for Full Custom VLSI Microcomputer Chips

    Publication Year: 1987 , Page(s): 364 - 373
    Cited by:  Papers (1)
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    This paper presents a practical CAD system application for layout and verification, resulting in producible full-cutom VLSI microcomputer chips. The CAD system supports three design methodologies--symbolic layout mixed with mask level layout, compaction as an optimizer, and fully automated verification. For the area optimization, the symbolic layout and compactor subsystem supports a flexible description of orthogonal layout patterns with arbitrary dimensions in a loose placement manner. The layout patterns include path data, polygonal data, and symbolic cells. For power and delay optimization, the compactor compacts layout data, decreasing both resistance and capacitance for wires and ion-implanted layers. This feature is pioneering the new generation compactor. Emphasis should be put on the fact that it can compact layout data to a format 10-15 percent smaller than that accomplished manually. The verification subsystem can detect all kinds of errors, more than 30 items. A novel feature of the electrical rule check is that it investigates complementary logic errors for CMOS circuits. The synergy of those three design methodologies has brought about several significant advantages. One is manpower reduction by more than half, in the most complicated design process for unique random logic. The other is a 1600-transistors compaction output, smaller by 365 mils2 than that manually compacted. The circuit implementation on a chip works at more than a 15-MHz clock rate. Another is the first silicon success. It has been accomplished in a full-custom VLSI microcomputer chip consisting of more than 100 000 transistors. View full abstract»

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  • Compaction-Based Custom LSI Layout Design Method

    Publication Year: 1987 , Page(s): 374 - 382
    Cited by:  Papers (1)
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    This paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size designed by using the proposed layout method is only 1.2-1.4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective for achieving a minimal chip layout design. View full abstract»

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  • A Block Interconnection Algorithm for Hierarchical Layout System

    Publication Year: 1987 , Page(s): 383 - 391
    Cited by:  Papers (5)  |  Patents (14)
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    A block interconnection algorithm for a general cell VLSI is described, which consists of a number of procedures such as a global router with signal delays taken into account, a router for power and ground, a block positioning scheme to minimize the chip size, a channel construction scheme with the use of L-shaped channels, and a grid-free channel router. The algorithm has been employed in a layout design system SMILE for general cell VLSI's for more than one year. Some of the experimental results are also shown. View full abstract»

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  • RFSIM: Reduced Fault Simulator

    Publication Year: 1987 , Page(s): 392 - 402
    Cited by:  Papers (9)
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    This paper describes the algorithm, implementation, and evaluation results of a new fault simulator called RFSIM, which is designed for combinational circuits. In order to accelerate fault simulation, two basic principles are introduced, a Detectable Fault Only (DFO) principle and a Candidate Gate Once (CGO) principle. The DFO principle is a dynamic reduction algorithm, which aims at drastically reducing computational complexity by utilizing blocking gate information. The CGO principle is an implementation technique which is utilized to implement the DFO principle effectively. Experimental results show that RFSIM is more than 10 times faster than a conventional concurrent fault simulator, and confirms that the DFO principle contributes to a drastic reduction in the number of faults to be simulated. A fault reduction ratio of around 25 to 1 was achieved in one of the benchmark circuits. View full abstract»

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  • Process Modeling for Photoresist Development and Design of DLR/sd (Double-Layer Resist by a Single Development) Process

    Publication Year: 1987 , Page(s): 403 - 409
    Cited by:  Papers (1)
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    This paper describes a new simple process model for photoresist development. The model includes the consideration of chemical reactions between a photoresist and a developer, and takes the developer concentration dependence into account. The model is applied to the design of practical photo-lithography processes to determine development conditions. Through the introduction of the model-based lithographic simulations, the multilayer resist process has been successfully designed and has obtained satisfactory patterns. View full abstract»

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  • A New Two-Dimensional Silicon Oxidation Model

    Publication Year: 1987 , Page(s): 410 - 416
    Cited by:  Papers (5)  |  Patents (2)
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    This paper describes a new two-dimensional silicon oxidation model taking into consideration the deformation of silicon. In the model based on the steady-state oxidant diffusion and viscoelastic deformation of the oxide, it is assumed that the oxide is composed of two layers during the deformation of the oxide. Simulated results on a LOCOS structure were obtained using the boundary element method (BEM). It is proved that the present model can analyze oxidation-induced stress in the silicon substrate, which is not explained by previous models, as well as predict the oxide shape. View full abstract»

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  • A Two-Dimensional Etching Profile Simulator: ESPRIT

    Publication Year: 1987 , Page(s): 417 - 422
    Cited by:  Papers (9)
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    A two-dimensional etching simulator named ESPRIT (FOOTNOTE: ESPRIT--Etching Simulation PRogram with an Improved sTring model.) has been developed to simulate LSI patterning. The etching simulator includes isotropic and anisotropic components. Its calculation method is based on the string model. ESPRIT can simulate etched profiles for multilayers with different etching rates and calculate side etching using sloped incidental anisotropic components. In addition, location correction, loop elimination, point insertion, and point elimination are provided for stable and accurate calculations. Simulated profiles coincide well with those from experiments in terms of relationship between the groove width and etched depth. ESPRIT can support to design LSI patterning process. View full abstract»

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  • Analysis of MOSFET Capacitances and Their Behavior at Short-Channel Lengths Using an AC Device Simulator

    Publication Year: 1987 , Page(s): 423 - 430
    Cited by:  Papers (7)
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    Intrinsic MOSFET capacitances are calculated using the three-dimensional ac device simulator CADDETH, and distributions of the internal ac currents are studied. The simulations clearly show the influence of velocity saturation. Finally short-channel effects on the intrinsic MOSFET capacitances are analyzed. View full abstract»

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  • A Three-Dimensional Photoresist Imaging Process Simulator for Strong Standing-Wave Effect Environment

    Publication Year: 1987 , Page(s): 431 - 438
    Cited by:  Papers (8)
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    The three-dimensional (3-D) photoresist imaging process simulator TRIPS-I has been improved to cope with the strong standing-wave effect in photoresists on flat substrate surfaces. To allow insertion of development vectors, which is necessary to advance photoresist-developer interface under the strong standing-wave effect, development vectors are calculated using the information of neighboring vectors. This information is recorded in units of triangles which are defined by tips of the three nearest development vectors. The triangular elements have also the advantage that precise expression is possible for complicated 3-D photoresist images resulting from a serious standing-wave effect. A photoresist image profile with a strong standing-wave effect showing good agreement with the actual photoresist image has been successfully simulated. In applications of TRIPS-I, photoresist patterns using lenses of different numerical apertures (NA's), 0.42 and 0.6, are compared. As a result, it is predicted that 0.3 X 0.3-μm hole patterns can be attained with the 0.6-NA lens. View full abstract»

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  • A Two-Dimensional Integrated Process Simulator: SPIRIT-I

    Publication Year: 1987 , Page(s): 439 - 445
    Cited by:  Papers (1)
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    A new two-dimensional integrated process simulation system named SPIRIT-I (Simulation Processor for Integrated Representation of Impurity-profile and Topography-I) has been developed. This system includes elementary process simulators of deposition, lithography, etching, ion implantation, diffusion, and oxidation. SPIRIT features a closely coupled simulation between a topography simulator and impurity-profile simulators at each processing step. As an example of simulation, an LDD (Lightly-Doped Drain) MOSFET with tilted source and drain implantation has been derived. In addition, this process simulation system is closely connected with a 3D device simulator. Using this coupled simulation system, the critical effect of processing conditions on device characteristics is analyzed. View full abstract»

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  • Two-Dimensional Simulation of Photolithography on Reflective Stepped Substrate

    Publication Year: 1987 , Page(s): 446 - 451
    Cited by:  Papers (5)
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    A new method for two-dimensional (2D) photolithography simulation is proposed. Lightwaves in photoresist are assumed to be polarized, and the layer beneath the photoresist is assumed to be a perfect conductor. In order to analyze lightwave behavior in a 2D region, Maxwell equations for electromagnetic fields are simplified into a Helmholtz equation which is solved in the photoresist region, taking lightwave damping in the infinite vacuum region surrounding the photoresist into account. The finite-element method and boundary-element method are used in the calculations. The bleaching model proposed by Drill et al. is applied to describe photoresist behavior on irradiation by exposure light. When this simulation is applied to a photoresist system on a reflective stepped surface, the simulated photoresist image is found to be in reasonably good agreement with an actually developed profile. View full abstract»

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  • A New Design-Centering Methodology for VLSI Device Development

    Publication Year: 1987 , Page(s): 452 - 461
    Cited by:  Papers (12)  |  Patents (1)
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    VLSI yield optimization and design centering are two key interests in the development of submicron VLSI's. Accordingly, we have developed a new design automation technique based on simulation CAD tools. The features of this methodology are great reduction of simulation time in device optimization, and accurate prediction of process sensitivity in device performance. The approach we used was basically a modification of the "design of experiment" method. This approach makes it possible to obtain an optimum design with a large number of design parameters. The methodology was successfully applied to the optimization of a 0.5-μm MOSFET structure based on only a one-day computation by a supercomputer (S-810) using a two-dimensional device simulator. In the design centering, we assumed five objective device performances, that is, threshold voltage VTH, output conductance GD, drain current ID, VTH dependence on gate length ΔVTH / ΔLG, and maximum substrate current I/ sub submax/. The use of the device design centering system predicted an optimized nMOSFET with 0.52-μm gate length, 9.4-nm gate oxide thickness, and 1.6 x 1016cm/sup-3/ substrate concentration for a given set of objective performances. Statistical variations of device characteristics were also calculated. View full abstract»

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  • A Permeation Router

    Publication Year: 1987 , Page(s): 462 - 471
    Cited by:  Papers (34)  |  Patents (1)
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    A permeation routing algorithm is proposed which decides the detailed routes on a new layout model. The permeation router attains a higher density by using the expanded routing region as well as the conventional one simultaneously. This routing algorithm consists of two phases. One is to partition the trunk set into three subsets corresponding to the trunks to be routed in the channel on the lower transistor row, upper transistor row, or between transistor rows. The other is to route these channels by using the one-layer channel assignment method as well as the conventional one. The experiments show that the routing results are practical and that the processing time is proportional to the number of trunks to the power of 1.4. View full abstract»

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  • WATOPT -- An Optimizer for Circuit Applications

    Publication Year: 1987 , Page(s): 472 - 479
    Cited by:  Papers (14)
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    A nonlinear constrained optimizer, WATOPT, targeted towards circuit applications is described. It utilizes a specially tailored quadratic program which reduces storage requirements and improves speed of computations. Three advanced designs in the frequency domain show application. View full abstract»

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  • Derivation of Signal Flow Direction in MOS VLSI

    Publication Year: 1987 , Page(s): 480 - 490
    Cited by:  Papers (34)  |  Patents (1)
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    This paper presents two sets of rules for deriving the direction of signal flow in MOS circuits. The first set works for a wide range of circuit designs in both nMOS and CMOS technologies because it is based on basic electrical and logical principles of circuit design. The second set contains design and technology specific heuristics. Together these rules yield the direction of signal flow through more than 99.9 percent of the transistors in four VLSI chips constructed in four different design styles. The application of derived signal directions in a timing verifier and electrical rules checker is also discussed View full abstract»

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  • Comments on "A Self-Consistent Monte-Carlo Particle Model to Analyze Semiconductor Microcomponents of any Geometry"

    Publication Year: 1987 , Page(s): 491
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    The intended purpose of a recent paper is questioned. Important references omitted from the paper are supplied. Various other aspects of the paper are commented upon. View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu