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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 2 • Date March 1987

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Displaying Results 1 - 17 of 17
  • Editorial

    Publication Year: 1987, Page(s): 157
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  • Editorial

    Publication Year: 1987, Page(s): 158
    Request permission for commercial reuse | PDF file iconPDF (208 KB)
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  • A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach

    Publication Year: 1987, Page(s):159 - 164
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    In this paper, we present a new approach for the one-dimensional gate assignment problem. The original minimization problem is transformed into a restricted problem, and then a new heuristic algorithm is applied to it. The solution obtained by the algorithm is interpreted as a solution for the original problem. The whole process of the approach has been implemented and tested with various examples... View full abstract»

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  • A Simple Yet Effective Technique for Global Wiring

    Publication Year: 1987, Page(s):165 - 172
    Cited by:  Papers (64)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1120 KB)

    A simple algorithm to perform global wiring is described. Repeated iterations of the algorithm tend to improve the quality of wiring by rerouting around congested areas. Various parameters can be set to give preference to short routes or to reduce the time taken by the algorithm. The algorithm has been tried out for several master-slice chips containing up to 3500 cells with good results. The tech... View full abstract»

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  • Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor Capacitances

    Publication Year: 1987, Page(s):173 - 184
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1784 KB)

    In order to analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree well. The causes of short-channel effects have been understood and explained by the simulations. Two-dimensional effects and velocity saturation are the main causes of short-channel ... View full abstract»

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  • Computer Simulation of Impurity Diffusion in Semiconductors by the Monte Carlo Method

    Publication Year: 1987, Page(s):185 - 189
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    A methodology of impurity diffusion in semiconductors by the Monte Carlo method has been presented. The simulation is carried out by repeating the motion of both vacancies and self-interstitials with the complementary weighting factor for the jumps of respective point defects. This method is applied to impurity diffusion from a limited source in a virtual semiconductor crystal and its validity is ... View full abstract»

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  • Single-Row Routing with Crossover Bound

    Publication Year: 1987, Page(s):190 - 201
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1760 KB)

    Previous studies of the single-row routing problem have been restricted to the minimization of the total number of horizontal tracks needed for the realization of a given set of nets. Therefore, it has been assumed that enough space exists between adjacent nodes to allow for the wiring. Due to this assumption, realizations obtained with previously proposed algorithms may require a large number of ... View full abstract»

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  • Symbolic Layout for Bipolar and MOS VLSI

    Publication Year: 1987, Page(s):202 - 210
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1320 KB)

    VLSI design requires design methodologies which are tailored to the implementation technology. Symbolic layout has been addressed in the past for MOS technology, while bipolar technology has largely been ignored. This paper describes a novel symbolic design technique which addresses both bipolar and MOS technologies. The technique allows the designer to symbolically layout nMOS, CMOS, and bipolar ... View full abstract»

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  • Thermodynamic Optimization of Block Placement

    Publication Year: 1987, Page(s):211 - 221
    Cited by:  Papers (19)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1584 KB)

    This paper presents the results of a systematic investigation of the thermodynamic ("simulated annealing") method applied to the placement of rectangular blocks on a chip. A new presentation of the fundamental ideas underlying this technique is proposed. It is shown that the analogies with physics, which have been at the origin of the method, may be partially forgotten, but that they are still use... View full abstract»

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  • On the Repair of Redundant RAM's

    Publication Year: 1987, Page(s):222 - 231
    Cited by:  Papers (56)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1344 KB)

    This paper describes a set of novel conditions that can be integrated in a computer-aided-testing (CAT) package for repair of redundant RAM's. A new approach is proposed; the innovative feature of this approach is the independence of analysis on the distribution of faulty bits in memory. This results in better exploitation of redundancy and efficient adaptability of this technique to various testi... View full abstract»

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  • Algorithms for an Advanced Fault Simulation System in MOTIS

    Publication Year: 1987, Page(s):232 - 240
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1400 KB)

    In this paper, we will present algorithms developed for an advanced fault simulation system in the MOTIS simulation environment. In particular, the algorithm to perform fault modeling and collapsing is first reviewed. Efficient algorithms to perform fault simulation are discussed in terms of fault list manipulation and primitive evaluation. The simulator realizes a speed gain factor of 787 to 2088... View full abstract»

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  • A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor

    Publication Year: 1987, Page(s):241 - 250
    Cited by:  Papers (22)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1376 KB)

    A new parallel-processing wire-routing algorithm is presented and implemented on a parallel processor. The two main features of the parallel algorithm are the control of the path quality and the finding of a quasi-minimum Steiner tree. Both Lee's maze algorithm and the proposed algorithm are implemented on an AAP-1 two-dimensional array processor, and the performance is compared to that of softwar... View full abstract»

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  • Switch-Level Logic Simulation of Digital Bipolar Circuits

    Publication Year: 1987, Page(s):251 - 258
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1128 KB)

    This paper describes a new approach for logic simulation of bipolar digital circuits. The approach is based on the development of a switch-level model of the transistor and on representing the circuit by a switch-graph. The method automatically partitions the circuit into subcircuits, and symbolic logic expressions are then generated which represent the logic states of the nodes in terms of subcir... View full abstract»

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  • Flamel: A High-Level Hardware Compiler

    Publication Year: 1987, Page(s):259 - 269
    Cited by:  Papers (81)  |  Patents (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1648 KB)

    This paper describes the design and implementation of a high-level hardware compiler called Flamel. Ordinary Pascal programs are used to define the behavior required of the hardware. Flamel undertakes to find parallelism in the program, so it can produce a fast-running implementation that meets a user-specified cost bound. A number of program transformations create sections of code with more paral... View full abstract»

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  • CMOS Circuit Speed and Buffer Optimization

    Publication Year: 1987, Page(s):270 - 281
    Cited by:  Papers (300)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1504 KB)

    An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. Essentially, the propagation delay is shown to be the sum of the s... View full abstract»

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  • Fully Dynamic Switch-Level Simulation of CMOS Circuits

    Publication Year: 1987, Page(s):282 - 289
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB)

    A new algorithm for switch-level simulation is suggested which allows the simulator to be fully dynamic, i.e., several signals may propagate in the network simultaneously. It is shown how this algorithm can be combined with a timing model. Finally, it is demonstrated how a simulator based on this algorithm can handle problems such as charge sharing and clock skewing in general CMOS circuits. View full abstract»

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  • Space Compression Methods With Output Data Modification

    Publication Year: 1987, Page(s):290 - 294
    Cited by:  Papers (48)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    The main advantages of space compression are the reduction in the number of pins monitored by the tester and the minimization of the memory space required for reference signatures. Compression, however, may reduce fault coverage. We investigate output data modification with the objective to improve the efficiency of syndrome testing and to reduce by a significant amount the error probability. It w... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu