IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 1 • January 1987

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Displaying Results 1 - 19 of 19
  • Editorial

    Publication Year: 1987, Page(s): 1
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  • Editorial

    Publication Year: 1987, Page(s):2 - 3
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  • A Predictor/CAD Model for Buried-Channel MOS Transistors

    Publication Year: 1987, Page(s):4 - 16
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1624 KB)

    An analytical predictor/CAD model for a short-channel buried-channel MOSFET is reported. The proposed model can be used to predict the anomalous threshold voltage shift associated with the short-channel buried-channel MOSFET. The characteristic is shown to be caused by the shifting of the operational mode from the surface to the buried channel. Current equations which are applicable to the short-c... View full abstract»

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  • A Ranking Algorithm for MOS Circuit Layouts

    Publication Year: 1987, Page(s):17 - 21
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    In the synthesis of digital circuits, one encounters the problem of identifying blocks which have been designed, so that there is no replication in the expensive effort of generating the physical layout of these blocks. We present a model for the synthesis of combinational logic into complex MOS circuits and present a ranking and unranking procedure to characterize the layout of each complex MOS c... View full abstract»

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  • A Systolic Design-Rule Checker

    Publication Year: 1987, Page(s):22 - 32
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1296 KB)

    We develop a systolic design-rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design-rule check phase of chip design. View full abstract»

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  • ADVIS: A Software Package for the Design of Systolic Arrays

    Publication Year: 1987, Page(s):33 - 40
    Cited by:  Papers (64)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1048 KB)

    A methodology for mapping numerical algorithms into systolic arrays is presented in this paper. This mapping is done using a transformation function which transforms the original sequential algorithm into a suitable parallel form. A program was developed to automatically generate this transformation. We consider both the case of arbitrarily large systolic arrays as well as the more realistic case ... View full abstract»

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  • An Extension to Newton's Method in Device Simulators--On An Efficient Algorithm to Evaluate Small-Signal Parameters and to Predict Initial Guess

    Publication Year: 1987, Page(s):41 - 45
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    The Newton iteration method used in conventional numerical device simulations is extended to include bias conditions as variable parameters in the system of semiconductor equations. This extension leads to a very simple algorithm to evaluate low-frequency, small-signal parameters based on dc solutions. It also provides an elegant way to project an initial guess for subsequent bias conditions. Rigo... View full abstract»

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  • Block-Level Hardware Logic Simulation Machine

    Publication Year: 1987, Page(s):46 - 54
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1344 KB)

    This paper describes a block-level hardware logic simulation machine. This is called a Hardware Logic Simulator (HAL). This paper first shows a block-level simulation method. Then, it overviews HAL hardware and software system configurations, and the simulation mechanism, and it estimates system performance. Finally, it discusses system applications and results. The paper also indicates that HAL h... View full abstract»

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  • Digraph Relaxation for 2-Dimensional Placement of IC Blocks

    Publication Year: 1987, Page(s):55 - 66
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1752 KB)

    A new graph-theoretic representation of the placement of rectangular IC blocks of arbitrary size and aspect ratio is proposed. This representation, called a relaxed digraph, provides an efficient model for two-dimensional calculations of minimum area layouts. Unlike other digraph models, the structure of the relaxed digraph represents an entire class of layout configurations derivable from a given... View full abstract»

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  • Efficient Algorithms for Layer Assignment Problem

    Publication Year: 1987, Page(s):67 - 78
    Cited by:  Papers (65)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2088 KB)

    The layer assignment problem for interconnect is the problem of determining which layers should be used for wiring the signal nets. The objective of the layer assignment problem in general is to minimize the number of vias required. Thus, it is also referred to as the via minimization problem. In a via minimization problem, if the topology of the given layout is fixed, the problem is referred to a... View full abstract»

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  • Exact and Approximate Solutions for the Gate Matrix Layout Problem

    Publication Year: 1987, Page(s):79 - 84
    Cited by:  Papers (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB)

    We consider the gate matrix layout problem for VLSI circuits, which is known to be NP-complete. We present an efficient algorithm for determining whether two tracks suffice. For the general problem of minimizing the number of tracks (and, hence, the area) needed, we design an attractive dynamic programming formulation to guarantee optimality. We also investigate the performance of fast heuristic a... View full abstract»

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  • Fast and Coherent Simulation with Zero Delay Elements

    Publication Year: 1987, Page(s):85 - 93
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1088 KB)

    This paper addresses the problem of event-directed logic simulation with part of the elements having zero delay. Incoherences arising from spikes having null duration (i.e., multiple transitions of a signal at a given simulation time, due to the simulation algorithm) are solved by a Two-Pass procedure, combining levelizing and event-driven simulation and yielding Ordered Activity Propagation. To o... View full abstract»

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  • Finding a Maximum Planar Subset of a Set of Nets in a Channel

    Publication Year: 1987, Page(s):93 - 94
    Cited by:  Papers (68)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    An algorithm is presented that, given N two-pin nets in a channel, finds, in O(N2) time, the largest subset that can be routed all on one layer View full abstract»

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  • Layering Algorithms For Single-Row Routing

    Publication Year: 1987, Page(s):95 - 102
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1128 KB)

    We develop two fast algorithms for the layering problem that arises when the single-row routing approach to wire layout is used. Both of these algorithms are for the case when the upper and lower street capacities are two. While neither of these algorithms guarantees the production of an optimal layering, it has been empirically determined that both will produce better layerings than an earlier pr... View full abstract»

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  • Linking the Behavioral and Structural Domains of Representation for Digital System Design

    Publication Year: 1987, Page(s):103 - 110
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1344 KB)

    A means of linking together the behavioral and structural domains of representation is presented. The approach can be used in a design synthesis system where the input is an abstract behavior of the system to be designed. As transformations are made to the behavior and the logical structure is specified, this approach maintains the correspondences between the two. These correspondences are maintai... View full abstract»

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  • Methodology Verification of Hierarchically Described VLSI Circuits

    Publication Year: 1987, Page(s):111 - 115
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    The standard approach to master the complexity of designing VLSI systems is to adopt a set of rules that, when respected, are conducive to correct implementations. Any such collection of rules can be called a design methodology. Most of the effort in computer-aided VLSI methodology verification has been traditionally concentrated on geometrical DRC. This paper describes a program that checks circu... View full abstract»

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  • Modeling and Description of Processor-Based Systems with DTMSII

    Publication Year: 1987, Page(s):116 - 127
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1472 KB)

    The aim of this new hardware description language, Descriptive Techniques for Modules and Systems II (DTMSII), is to enhance mixed level descriptions and multilevel modeling of interconnected digital systems [1][2][3]. The focus in DTMSII is on the description of the functional behavior of digital modules coupled with a detailed description of module interactions. Processor and related modules can... View full abstract»

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  • Network Partitioning and Ordering for MOS VLSI Circuits

    Publication Year: 1987, Page(s):128 - 144
    Cited by:  Papers (13)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2560 KB)

    This paper describes the algorithms used in a presimulation phase to partition an MOS digital network into various special subnetworks (or blocks) and to order these subnetworks for processing in a switch-level timing simulator such as MOSTIM [1]. A transistor-level SPICE2-type [3] description of the network is assumed to be provided. The key to the partitioning strategy is to divide the set of en... View full abstract»

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  • The Outline Procedure in Pattern Data Preparation for Vector-Scan Electron-Beam Lithography

    Publication Year: 1987, Page(s):145 - 151
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB)

    This paper describes a new algorithm and some applications of an outline procedure for LSI mask patterns. The outline procedure, which extracts the outline of designed primitive shapes, is required in pattern data preparation for electron-beam (e-beam) writing. A novel algorithm is developed to extract the outlines of patterns from a large number of designed shapes within a whole chip area. The al... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu