IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • October 1986

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Displaying Results 1 - 23 of 23
  • Foreword

    Publication Year: 1986, Page(s): 449
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  • SLS: An Advanced Symbolic Layout System for Bipolar and FET Design

    Publication Year: 1986, Page(s):450 - 458
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1224 KB)

    This paper describes features of the Symbolic Layout System (SLS), an advanced layout system for VLSI designs. Symbolic layout is a method by which point objects, wires, and regions are sketched on a virtual grid, converted to shapes, and then spaced according to a set of minimum ground rules using a compactor. Point objects are defined as terminals, FET transistors, contacts, or vias. These objec... View full abstract»

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  • Glitter: A Gridless Variable-Width Channel Router

    Publication Year: 1986, Page(s):459 - 465
    Cited by:  Papers (63)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (968 KB)

    In the traditional approach to channel routing, terminals must be located on grid points and wire segments must be placed on grid lines. Without using the grids, we can take advantage of the two interconnection layers with variable wire width and spacing. Terminals are no longer required to be on grids, and nets may even have different wire widths. The new gridless approach which we propose is bas... View full abstract»

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  • A Hardware Maze Router with Application to Interactive Rip-Up and Reroute

    Publication Year: 1986, Page(s):466 - 476
    Cited by:  Papers (32)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1624 KB)

    This paper presents a new parallel-processing architecture for hardware routers based on the Lee algorithm. Unlike the existing machines, which require N2 processors to implement the Lee algorithm on an N x N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 x 128 ... View full abstract»

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  • Mason: A Global Floorplanning Approach for VLSI Design

    Publication Year: 1986, Page(s):477 - 489
    Cited by:  Papers (72)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2264 KB)

    A global floorplanning approach is presented which allows designers to quickly explore layout issues during the initial stages of the IC design process. The approach is based on a combined mincut and slicing paradigm, in an effort to ensure routability. A slicing-tree representation is employed, upon which efficient traversal operations are applied resulting in area-efficient floorplans. The metho... View full abstract»

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  • SPARTA: A System Partitioning Aid

    Publication Year: 1986, Page(s):490 - 498
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1040 KB)

    This paper presents SPARTA, the System PARTitioning Aid. Partitioning is the design phase in which a system's functionality is divided into smaller parts that fit onto physical units. SPARTA is a unique and interesting approach to computer-aided partitioning of systems SPARTA performs the tedious calculation of each design factor (such as area) for each partition (such as chips). This allows the d... View full abstract»

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  • A Meyer-Like Approach for the Transient Analysis of Digital MOS IC's

    Publication Year: 1986, Page(s):499 - 507
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1128 KB)

    It is well known that Meyer's model for the MOST implemented in SPICE does not guarantee charge conservation, while Ward's model seems somewhat complex to be used as a standard for the transient analysis of all the MOS circuits. In this work, a new simple MOST model for the transient analysis of MOS integrated circuits is presented. The model was developed by performing the numerical integration o... View full abstract»

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  • A Statistical Design Rule Developer

    Publication Year: 1986, Page(s):508 - 520
    Cited by:  Papers (19)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2080 KB)

    In this paper, a general methodology for design rule development and the CAD tool which implements this methodology, Statistical Design Rule Developer (STRUDEL), are presented. The focus of the proposed approach is the concept of a statistical design rule, which is defined as a geometric design rule with an associated probability of failure. Global lateral variations obtained from FABRICS, and loc... View full abstract»

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  • Simulation of Nonlinear Circuits in the Frequency Domain

    Publication Year: 1986, Page(s):521 - 535
    Cited by:  Papers (272)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2216 KB)

    Simulation in the frequency domain avoids many of the severe problems experienced when trying to use traditional time-domain simulators such as SPICE to find the steady-state behavior of analog and microwave circuits. In particular, frequency-domain simulation eliminates problems from distributed components and high-Q circuits by foregoing a nonlinear differential equation representation of the ci... View full abstract»

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  • A Fast-Timing Simulator for Digital MOS Circuits

    Publication Year: 1986, Page(s):536 - 540
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (792 KB)

    An efficient and accurate algorithm has been developed for predicting the timing waveforms of general MOS transistor circuits. The algorithm uses a switch-level simulation technique to determine the steady-state conditions, a forward prediction method to predict the transient time between two adjacent voltage levels, a simplified timing simulation technique to correct this delay, and novel approac... View full abstract»

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  • VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits

    Publication Year: 1986, Page(s):541 - 556
    Cited by:  Papers (178)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2568 KB)

    This paper describes the yield simulator VLASIC (VLSI Layout Simulation for Integrated Circuits). VLASIC is a Monte Carlo simulator that uses defect models and statistics to place random catastrophic point defects on a chip layout and determine what circuit faults, if any, have occurred. The defect models are described in tables, and so are readily extended to new processes or defect types. The de... View full abstract»

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  • FAUST: An MOS Fault Simulator with Timing Information

    Publication Year: 1986, Page(s):557 - 563
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1024 KB)

    This paper describes FAUST, an MOS fault simulator with timing information. FAUST simulates the effects of realistic physical failures on MOS circuits and uses a static concurrent fault-simulation technique to evaluate the fault-free circuit and all the faulty circuits in one pass. FAUST produces voltage waveforms as well as logic tables with delay information for the fault-free circuit and for ea... View full abstract»

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  • Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits

    Publication Year: 1986, Page(s):564 - 572
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1416 KB)

    In this paper, we analyze combinational logic circuits using "fan-out constraints" to generate tests for single stuck-at faults. A method of circuit transformation is employed to explicitly derive "fan-out constraints for controllability" and "fan-out constraints for observability," which are dependent Boolean functions and Boolen difference functions, respectively, in terms of primary inputs and ... View full abstract»

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  • C-Testability of Two-Dimensional Iterative Arrays

    Publication Year: 1986, Page(s):573 - 581
    Cited by:  Papers (74)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1184 KB)

    The issue of testing two-dimensional iterative arrays with a constant number of test vectors independent of the array size (C-testability) is discussed in this paper. Sufficient conditions for C-testability are stated. It is shown that any two-dimensional array can be modified to become C-testable. An extension to systolic (synchronous) arrays is made. The approach simplifies testing systolic arra... View full abstract»

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  • Synthesis and Optimization of Multilevel Logic under Timing Constraints

    Publication Year: 1986, Page(s):582 - 596
    Cited by:  Papers (57)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2424 KB)

    The automation of the synthesis and optimization of combinational logic can result in savings in design time, significant improvements of the circuitry, and guarantee functional correctness. Synthesis quality is often measured in terms of the area of the circuit on the chip, which fails to take into account the timing constraints that might be imposed on the logic. This paper describes SOCRATES, a... View full abstract»

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  • Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros

    Publication Year: 1986, Page(s):597 - 616
    Cited by:  Papers (70)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3312 KB)

    This paper presents a method for the optimal synthesis of combinational and sequential circuits implemented by two-level logic macros, such as programmable logic arrays. Optimization consists of finding representations of switching functions corresponding to minimal-area implementations. The design of optimization is based on two steps: symbolic minimization and constrained encoding. Symbolic mini... View full abstract»

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  • Concurrency and Communication in Hardware Simulators

    Publication Year: 1986, Page(s):617 - 623
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (936 KB)

    This paper describes models for concurrency and interpartition communication in a hardware logic simulator implemented using multiprocessors. Software simulation data from production VLSI chips were analyzed in the context of a multiprocessor environment to obtain experimental values for concurrency and communication. The VLSI chips were randomly partitioned in the above experiments. The concurren... View full abstract»

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  • Table Lookup MOSFET Capacitance Model for Short-Channel Devices

    Publication Year: 1986, Page(s):624 - 632
    Cited by:  Papers (16)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (888 KB)

    A charge-based table lookup MOSFET capacitance model is derived for a circuit simulation application. Measured Cgs(Vds, Vgs) and Cgd(Vds, Vgs) tables and a calculated Q(Vds, Vgs) table are utilized for representing nonlinear MOSFET capacitance behavior. The substrate terminal effect for Cgs and C View full abstract»

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  • PLATYPUS: A PLA Test Pattern Generation Tool

    Publication Year: 1986, Page(s):633 - 644
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2016 KB)

    PLATypus (PLA Test pattern generation and logic simulation tool) is an efficient tool for large PLA's which is interfaced with other existing PLA tools such as the folding program PLEASURE [12] and the logic minimizer ESPRESSO II-C [11] developed at the University of California at Berkeley. A new algorithm is proposed based on complementation and the tautology check of a logic cover, derived from ... View full abstract»

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  • MONTE: A Program to Simulate the Heterojunction Devices in Two Dimensions

    Publication Year: 1986, Page(s):645 - 652
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1248 KB)

    This paper describes the two-dimensional heterojunction device simulator MONTE. Drift-diffusion forms the basis for the transport of electrons and holes. Finite differences and Gummel's algorithm have been adopted to solve the coupled equations. Internal electrodes, capping dielectrics, recessed gates, Fermi-level pinning at the device surface, and deep traps in the substrate can all be treated. A... View full abstract»

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  • SPICE Simulation of SOI MOSFET Integrated Circuits

    Publication Year: 1986, Page(s):653 - 658
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (984 KB)

    A five-terminal, charge-based model for the thin-film silicon-on-insulator (SOI) MOSFET is implemented in SPICE2, thereby enabling, for the first time, proper simulation and CAD of SOI MOS integrated circuits in which the unique floating-body and back-gate-bias effects can be significant. The implementation is achieved, without having to rewrite the circuit simulator, by developing a general metho... View full abstract»

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  • Macromodeling and Optimization of Digital MOS VLSI Circuits

    Publication Year: 1986, Page(s):659 - 678
    Cited by:  Papers (68)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3160 KB)

    Power consumption and signal delay are crucial to the design of high-performance VLSI circuits. This paper presents CAD tools for modeling and optimizing digital MOS designs. The tools determine the transistor sizes that minimize circuit power consumption subject to constraints on signal path delays. Computational efficiency is obtained through macromodeling techniques and a specialized optimizati... View full abstract»

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  • Ion Implantation Calculations in Two Dimensions Using the Boltzmann Transport Equation

    Publication Year: 1986, Page(s):679 - 684
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (744 KB)

    A two-dimensional method based on numerical solution of the Boltzmann transport equation has been developed for calculating ion implantation profiles. The method is capable of treating arbitrarily contoured surfaces containing multiple layers of different materials. Calculations yield the concentration profile of the implanted ion, an estimate of the damage distribution, and concentration profiles... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu