IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 3 • July 1985

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Displaying Results 1 - 21 of 21
  • Editorial

    Publication Year: 1985, Page(s): 165
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  • Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits

    Publication Year: 1985, Page(s):166 - 177
    Cited by:  Papers (128)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2032 KB)

    In this paper, a modeling technique, describing IC manufacturing yield losses in terms of parameters characterizing lithography related point defects and line registration errors, is presented. Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling techn... View full abstract»

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  • BAMBI -- A Design Model for Power MOSFET's

    Publication Year: 1985, Page(s):177 - 189
    Cited by:  Papers (31)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1808 KB)

    Numerical simulation models are utilized for the development and the design of semiconductor devices to a steadily growing extent. However, the simulation programs to date are known only to be handled under some restrictions. This paper presents the novel program system BAMBI, capable of simulating the two-dimensional transient behavior of arbitrarily shaped devices. The exact numerical model acco... View full abstract»

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  • Routing Region Definition and Ordering Scheme for Building-Block Layout

    Publication Year: 1985, Page(s):189 - 197
    Cited by:  Papers (56)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1400 KB)

    We present a new routing region definition and ordering (RRDO) scheme for building block layout. Given an arbitrary placement of rectangular blocks (including the case with cycles in the channel precedence constraints), without modifying the placement, our scheme defines and orders channels so that when a new channel is being routed, its width can be expanded or contracted without destroying the p... View full abstract»

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  • Two-Dimensional Routing for the Silc Silicon Compiler

    Publication Year: 1985, Page(s):198 - 203
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (888 KB)

    This paper presents a new method for generating a two-dimensional routing for a class of custom integrated circuits (IC's). The method has been designed for Silc, an experimental silicon compiler currently under development at GTE Laboratories, and is suitable for the design of custom IC's composed of functional blocks. The method is based on an analytical model for generating a one-dimensional di... View full abstract»

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  • Efficient Algorithms for Routing Interchangeable Terminals

    Publication Year: 1985, Page(s):204 - 207
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (464 KB)

    This paper presents new algorithms for routing two rows of interchangeable terminals across a 2-layer channel. The number of horizontal tracks required for routing is significantly reduced by simply interchanging terminals in each cell. Savings up to one-third of horizontal tracks or more are achieved by interchanging terminals. The Deutsch Difficult Example is used as a test routing problem. The ... View full abstract»

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  • A New Symbolic Channel Router: YACR2

    Publication Year: 1985, Page(s):208 - 219
    Cited by:  Papers (109)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1832 KB)

    YACR2 is a channel router that minimizes the number of through vias in addition to the area used to complete the routing in a two-layer channel. It can route channels with cyclic constraints and uses a virtual grid. YACR2 uses preferably one layer for the horizontal segments of the nets and the other for the vertical ones but it may require the routing of a few horizontal segments in the second la... View full abstract»

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  • Gate Matrix Layout

    Publication Year: 1985, Page(s):220 - 231
    Cited by:  Papers (62)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1472 KB)

    A graph-theoretic description of the problem of layout of CMOS circuits in the style of gate matrix in minimum area is presented. The problem is formulated as one of finding two assignment functions f and h such that the layout L(f, h) requires the minimum number of rows of the gate matrix. The function f maps the distinct gates of the transistors to the columns of the gate matrix and the function... View full abstract»

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  • Vectorized LU Decomposition Algorithms for Large-Scale Circuit Simulation

    Publication Year: 1985, Page(s):232 - 239
    Cited by:  Papers (20)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1240 KB)

    Proposed here are two kinds of vectorized LU decomposition algorithms for an unstructured sparse matrix arising from large scale circuit simulation. Either algorithm implemented on our supercomputer S810 improves efficiency 11 to 82 times for LU decomposition and 2.1 to 8.9 times in total simulation, as compared with a conventional algorithm. Both algorithms detect operational parallelism in the i... View full abstract»

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  • A Hardware Architecture for Switch-Level Simulation

    Publication Year: 1985, Page(s):239 - 250
    Cited by:  Papers (13)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2128 KB)

    The Mossim Simulation Engine (MSE) is a hardware accelerator for performing switch-level simulation of MOS VLSI circuits [1], [2]. Functional partitioning of the MOSSIM algorithm and specialized circuitry are used by the MSE to achieve a performance improvement of > 300 over a VAX 11/780 executing the MOSSIM II program. Several MSE processors can be connected in parallel to achieve additional s... View full abstract»

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  • The S-Algorithm: A Promising Solution for Systematic Functional Test Generation

    Publication Year: 1985, Page(s):250 - 263
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2272 KB)

    We present a new algorithm for functional test generation of VLSI systems. This algorithm for functional test generation for each testable register-transfer (RT) level fault defined in our established fault model. The technique developed is appropriate for test generation in top-down Computer-Aided Design process. The development of the algorithm is based on two foundations: the RT-level fault mod... View full abstract»

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  • Design of Testable CMOS Logic Circuits Under Arbitrary Delays

    Publication Year: 1985, Page(s):264 - 269
    Cited by:  Papers (44)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1024 KB)

    The sequential behavior of CMOS logic circuits in the presence of stuck-open faults requires that an initialization input followed by a test input be applied to detect such a fault. However, a test set based on the assumption that delays through all gates and interconnections are zero, can be invalidated in the presence of arbitrary delays in the circuit. In this paper, we will present a necessary... View full abstract»

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  • Optimal State Assignment for Finite State Machines

    Publication Year: 1985, Page(s):269 - 285
    Cited by:  Papers (205)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2552 KB)

    Computer-Aided synthesis of sequential functions of VLSI systems, such as microprocessor control units, must include design optimization procedures to yield area-effective circuits. We model sequential functions as deterministic synchronous Finite State Machines (FSM's), and we consider a regular and structured implementation by means of Programmable Logic Arrays (PLA's) and feedback registers. St... View full abstract»

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  • An Integrated Automated Layout Generation System for DSP Circuits

    Publication Year: 1985, Page(s):285 - 296
    Cited by:  Papers (48)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2032 KB)

    An integrated CAD system for the automated design of digital signal-processing (DSP) circuits for audio and telecommunication applications is described. The system uses as unique input a symbolic description of algorithm. This representation is translated into an actual layout using a two-step process. First, the symbolic input is mapped into the target architecture, which consists basically of a ... View full abstract»

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  • AROMA: An Area Optimized CAD Program for Cascade SC Filter Design

    Publication Year: 1985, Page(s):296 - 303
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1280 KB)

    An area optimized computer-aided cascade switched-capacitor (SC) filter design program called AROMA is presented. The program contains several user-selectable filter approximation techniques. AROMA permits the user to make tradeoffs between several design parameters such as passive sensitivity, op-amp output voltage swings, clock frequency, and the total capacitance of the filter. The program has ... View full abstract»

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  • DIALOG: An Expert Debugging System for MOSVLSI Design

    Publication Year: 1985, Page(s):303 - 311
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1280 KB)

    An expert system (DIALOG) is described to check correctness of logic levels and timing composition rules in n- or CMOS VLSI logic. Knowledge is described in an engineer oriented language (LEXTOC) allowing for unification (cfr PROLOG), object creation, property assignment, association of relations, rule formulation, logic or arithmetic evaluation as well as conversational constructs. The system is ... View full abstract»

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  • A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits

    Publication Year: 1985, Page(s):312 - 321
    Cited by:  Papers (54)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1520 KB)

    This paper proposes a new logical model for nMOS and CMOS circuits. Existing gate-level and switch-level models are limited in their ability to simulate MOS circuit behavior accurately when modeling physical failures. The model proposed in this paper is in the form of a multivalued algebra defined on a set of node states. The state of a node is represented as a pair <a,b> where "a" specifies... View full abstract»

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  • A Simulation Method to Completely Model the Various Transistor I-V Operational Modes of Long Channel Depletion MOSFET's

    Publication Year: 1985, Page(s):322 - 328
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (920 KB)

    It is known that a depletion MOS device behaves quite differently from an enhancement device. Because of its intrinsic difference, depletion I-V characteristics are much more complicated than are the I-V functions of an enhancement MOSFET. The conventional transistor I-V equation developed for enhancement transistors cannot be applied directly to depletion transistors. In this paper, seven operati... View full abstract»

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  • A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays

    Publication Year: 1985, Page(s):329 - 336
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1272 KB)

    The channel router, which routes a rectangular channel with two rows of terminals along its top and bottom sides, is extensively used for the automatic routing of gate arrays. It is well known that in this routing method the routing can not be performed when the vertical constraint graph contains cycles. This paper deals with the problem of eliminating cycles in the vertical constraint graph by in... View full abstract»

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  • A Switch-Level Timing Verifier for Digital MOS VLSI

    Publication Year: 1985, Page(s):336 - 349
    Cited by:  Papers (165)  |  Patents (23)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2520 KB)

    Crystal is a timing verification program for digital nMOS and CMOS circuits. Using the circuit extracted from a mask set, the program determines the length of each clock phase and pinpoints the longest paths. Crystal can process circuits with about 40 000 transistors in about 20-30 min of VAX-11/780 CPU time. The program uses a switch-level approach in which the circuit is decomposed into chains o... View full abstract»

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  • A Physical and SPICE-Compatible Model for the MOS Depletion Device

    Publication Year: 1985, Page(s):349 - 356
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1112 KB)

    An MOS depletion device model that is compatible with SPICE circuit simulation program and based on device physics is described. The depletion device is modeled by an equivalent circuit consisting of various well-characterized semiconductor devices, for example, the enhancement MOS device and the JFET. IT has the advantages of both the existing physical and empirical models. The model is applicabl... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu