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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 1 • January 1985

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Displaying Results 1 - 13 of 13
  • Remarks as Outgoing Editor

    Publication Year: 1985, Page(s): 1
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  • Introduction

    Publication Year: 1985, Page(s): 2
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  • Automatic Design for Testability Via Testability Measures

    Publication Year: 1985, Page(s):3 - 11
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1280 KB)

    In this paper we present a technique for the automatic design for testability of digital circuits based upon the analysis of controllability and observability measures. The new concept of sensitivity is introduced, which is a measure for the degree to which the testability of a circuit improves as increased controllability and observability is achieved over a set of nodes in a circuit. In order to... View full abstract»

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  • CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design

    Publication Year: 1985, Page(s):12 - 22
    Cited by:  Papers (53)  |  Patents (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1672 KB)

    In a hierarchical VLSI layout design, the block-level layout design is called a "chip floor plan." In this paper, a semi-automatic VLSI chip floor plan algorithm and its implementation are presented. The initial block placement is obtained by an attractive and repulsive force method (AR method), and the subsequent block packing process is performed by gradually moving and reshaping blocks with chi... View full abstract»

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  • Channel Routing Algorithms for Overlap Models

    Publication Year: 1985, Page(s):23 - 30
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1152 KB)

    We consider routing models that consist of L layers in which each layer can contain horizontal and vertical wires and in which up to k wires on different layers are allowed to run on top of each other. Within this overlap model we study the relationship between the channel width, the number of contact points, and the amount of overlap used for routing n two-terminal nets across a channel. For k &#... View full abstract»

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  • Dogleg Channel Routing is NP-Complete

    Publication Year: 1985, Page(s):31 - 41
    Cited by:  Papers (113)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1776 KB)

    Interconnecting two rows of points across an intervening channel is an important problem in the design of LSI circuits. The most common methodology for producing such interconnections uses two orthogonal layers of parallel conductors and allows wires to "dogleg" arbitrarily. Although effective heuristic procedures are available for routing channels with this methodology, no efficient optimal algor... View full abstract»

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  • Finite-Element Simulation of Local Oxidation of Silicon

    Publication Year: 1985, Page(s):41 - 53
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1824 KB)

    In this paper, various numerical models for finite element simulation of local oxidation of silicon are investigated. The simplest one contains linear diffusion of oxidizing species and elastic displacements of dioxide layers. The limitations of this model and the influences of pad-oxide and nitride mask thicknesses as well as temperature are illustrated by computer simulations. The local effects ... View full abstract»

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  • Geographical Data Structures Compared: A Study of Data Structures Supporting Region Queries

    Publication Year: 1985, Page(s):53 - 67
    Cited by:  Papers (56)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1904 KB)

    This paper compares three data structures that support area operations on 2-space: linked lists, quad trees, and multidimensional binary trees (k-d trees). Region searching is the most important operation these data structures must support in many applications. Insertion and deletion must also be reasonably fast. The three data structures are described and implementation considerations are discuss... View full abstract»

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  • A Linear-Time Routing Algorithm for Convex Grids

    Publication Year: 1985, Page(s):68 - 76
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1312 KB)

    In this paper, we consider the channel routing problem involving two-terminal nets on rectilinear grids. An efficient algorithm is described which necessarily finds a routing in a given grid whenever it exists. The algorithm is not a heuristic but an exact one, and works for a rather large class of grids, called convex grids, including the grids of rectangular, T-, L-, or X-shape boundaries. Both ... View full abstract»

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  • A Pattern Recognition Based Method for IC Failure Analysis

    Publication Year: 1985, Page(s):76 - 92
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2568 KB)

    Random fluctuations which are inherent in the IC manufacturing process cause production yields to be significantly less than 100 percent. Yield drop is caused by two types of faults, catastrophic and parametric. This paper deals with the diagnosis of parametric faults which occur during the manufacturing of IC's and cause the yield to drop below some acceptable level. A statistical pattern recogni... View full abstract»

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  • A Procedure for Placement of Standard-Cell VLSI Circuits

    Publication Year: 1985, Page(s):92 - 98
    Cited by:  Papers (256)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (992 KB)

    This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production us... View full abstract»

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  • Technology Independent Device Modeling for Simulation of Integrated Circuits for FET Technologies

    Publication Year: 1985, Page(s):99 - 110
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1696 KB)

    A novel approach to device modeling for circuit simulation of integrated circuits is presented. This approach is based on general nonlinear network models in tensor product spline representation. As a consequnce this device modeling approach is technology independent and automatable. Tensor product spline representations of nonlinear branch elements are particularly useful, since the controlling v... View full abstract»

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  • Three-Dimensional Monte Carlo Simulations--Part II: Recoil Phenomena

    Publication Year: 1985, Page(s):110 - 117
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1056 KB)

    A Monte Carlo method has been applied to recoil calculation. The spatial distribution of disorder has been analyzed in connection with parameters like ion mass, energy, and dose. Also implants in multilayer targets and the characteristic features of oxygen recoiling from a SiO 2 coating into Si underneath have been analyzed. View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu