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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • October 1984

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Displaying Results 1 - 7 of 7
  • An Approximation Problem for the Multi-Via Assignment Problem

    Publication Year: 1984, Page(s):257 - 264
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1240 KB)

    We consider the multi-via assignment problem for multilayered printed circuit board routing. An efficient approximation algorithm for this problem is presented. The algorithm is of (low) polynomial time complexity and guarantees solutions with no more than 3 * OPT via columns, where OPT is the number of via columns in an optimal solution. Several issues relating to the computational complexity of ... View full abstract»

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  • A Class of Cellular Architectures to Support Physical Design Automation

    Publication Year: 1984, Page(s):264 - 278
    Cited by:  Papers (21)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2480 KB)

    Special-purpose hardware has been proposed as a solution to several increasingly complex problems in design automation. This paper examines a class of cellular architectures called raster pipeline subarrays--RPS architectures--applicable to problems in physical DA that are (1) representable on a cellular grid, and (2) characterized by local functional dependencies among grid cells. Machines with t... View full abstract»

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  • An Extrapolated Yield Approximation Technique for Use in Yield Maximization

    Publication Year: 1984, Page(s):279 - 287
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1416 KB)

    This paper is concerned with the computational problem of maximizing the yield of circuits. A statistical Monte Carlo based approach is taken in order to compute yield estimates directly and to decrease dimensionality dependence. The main contribution of this paper is a yield extrapolation technique which is very effective in maximizing the yield along a search direction. This technique is based u... View full abstract»

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  • Chip Level Modeling of LSI Devices

    Publication Year: 1984, Page(s):288 - 297
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1472 KB)

    The advent of Very Large Scale Integration (VLSI) technology has rendered the gate level model impractical for many simulation activities critical to the design automation process. As an alternative, an approach to the modeling of VLSI devices at the chip level is described, including the specification of modeling language constructs important to the modeling process. A model structure is presente... View full abstract»

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  • Global Routing for Gate Array

    Publication Year: 1984, Page(s):298 - 307
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1544 KB)

    We propose a new approach to the global routing of gate arrays. The method can handle any channel capacities and pin distributions on the chip. The global router first finds unique routes, then pushes connections to the periphery. As outer wiring capacity is consumed, the routing continues inward, connecting pins and making global cell assignments for nets by a centrifugal layering process. The go... View full abstract»

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  • Relaxation-Based Electrical Simulation

    Publication Year: 1984, Page(s):308 - 331
    Cited by:  Papers (100)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4120 KB)

    Circuit simulation programs have proven to be most important computer-aided design tools for the analysis of the electrical performance of integrated circuits. One of the most common analyses performed by circuit simulators and the most expensive in terms of computer time is nonlinear time-domain transient analysis. Conventional circuit simulators were designed initially for the cost-effective ana... View full abstract»

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  • Signal Delay in General RC Networks

    Publication Year: 1984, Page(s):331 - 349
    Cited by:  Papers (114)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2392 KB)

    Based upon the delay of Elmore, a single value of delay is derived for any node in a general RC network. The effects of parallel connections and stored charge are properly taken into consideration. A technique called tree decomposition and load redistribution is introduced that is capable of dealing with general RC networks without sacrificing a number of desirable properties of tree networks. An ... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu