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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 3 • July 1984

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Displaying Results 1 - 13 of 13
  • A Computational Approach for the Diagnosability of Dynamical Circuits

    Publication Year: 1984, Page(s):165 - 171
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1120 KB)

    Based on a discrete-time circuit description, a necessary and sufficient condition is derived for the local diagnosability of the class of dynamical circuits whose branch relations are analytic functions of their arguments. Both the single-fault case and the case where all the parameters are assumed to be faulty are dealt with. The condition is a rank test on a matrix that is determined from a sin... View full abstract»

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  • A Hierarchical Standard Cell Approach for Custom VLSI Design

    Publication Year: 1984, Page(s):172 - 177
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB)

    A custom VLSI design technique, using an integrated CAD system is described. The design system features on the hierarchical design process and layout design capability by system designers (customers). As for application, high-performance LSI's for 16-bit CPU were developed. The LSI design was accomplished in a short period (three months with three designers) due to the hierarchical standard cell a... View full abstract»

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  • An Efficient Single-Row Routing Algorithm

    Publication Year: 1984, Page(s):178 - 183
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    In this paper, we present a heuristic algorithm for single-row routing. Our approach is based on the interval graphical representation of the given net list. The objective function for minimization is the street congestion. The problem is known to be intractable in the sense of NP-completeness, thus a polynomial-time heuristic algorithm is proposed. It has been implemented and tested with various ... View full abstract»

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  • An Unconstrained Topological Via Minimization Problem for Two-Layer Routing

    Publication Year: 1984, Page(s):184 - 190
    Cited by:  Papers (66)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB)

    Based on graph theory, a study of via minimization problem is presented. We show that the simplest problem of this type is NP-complete and propose a heuristic algorithm for topological via minimization. View full abstract»

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  • Bipartite Folding and Partitioning of a PLA

    Publication Year: 1984, Page(s):191 - 199
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1488 KB)

    A more restricted definition of a PLA folding is introduced, which is called bipartite folding. The additional constraints of a bipartite folding force the resulting PLA to have a more uniform structure. This structure of a column bipartite folding is then exploited when subsequently folding the rows of the PLA. A column bipartite folding creates fewer constraints upon the ability to fold the rows... View full abstract»

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  • Fault Modeling for Digital MOS Integrated Circuits

    Publication Year: 1984, Page(s):200 - 208
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1360 KB)

    A new fault modeling technique aimed at efficient simulation and test generation for complex digital MOS IC's is described. It is based on connector-switch-attenuator (CSA) analysis, which employs purely digital models of switching transistors, resistive/capacitive elements, and their associated signals. The use of CSA networks to model the digital behavior, both static and dynamic, of MOS circuit... View full abstract»

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  • Hardware Compilation from an RTL to a Storage Logic Array Target

    Publication Year: 1984, Page(s):208 - 217
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1592 KB)

    This paper treats the automatic translation of register transfer level (RTL) descriptions of digital systems to VLSI realization. The target technology is the storage logic array or SLA. The approach is aimed at applications where the emphasis is on reducing engineering effort and design turnaround time rather than maximizing chip area utilization. The paper develops a mapping between the register... View full abstract»

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  • Module Placement Based on Resistive Network Optimization

    Publication Year: 1984, Page(s):218 - 225
    Cited by:  Papers (104)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1208 KB)

    A new constructive placement and partitioning method based on resistive network optimization is proposed. The objective function used is the sum of the squared wire length. The method has the feature which includes fixed modules in the formulation. The overall algorithm comprises the following subprograms: optimization, scaling, relaxation, partitioning and assignment. The method is efficient beca... View full abstract»

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  • Quasi-Static Control of Explicit Algorithms for Transient Analysis

    Publication Year: 1984, Page(s):226 - 234
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1080 KB)

    A linearized state-variable formulation of the lumped circuit simulation problem shows the results of some simpler related dc analyses to be useful in the time step size stability control of explicit integration algorithms. These analyses result also in a stable explicit integration algorithm that is often applicable. Because the various results obtained are amenable to simple physical interpretat... View full abstract»

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  • Single-Row Routing in Narrow Streets

    Publication Year: 1984, Page(s):235 - 241
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (896 KB)

    We develop fast linear time algorithms for single row routing when the upper and lower street capacities are less than or equal to three. A similarly fast algorithm is developed for the case when one of the streets has a capacity 1 and the other has an arbitrary capacity. Experimental results show that our algorithms are many times faster than previously developed algorithms. View full abstract»

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  • The User Interface and Implementation of an IC Layout Editor

    Publication Year: 1984, Page(s):242 - 249
    Cited by:  Papers (10)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1384 KB)

    This paper describes several novel aspects of Caesar, a layout editor for Manhattan-style integrated circuits. The program's user interface is similar to painting. By hiding many irrelevant details, the painting mechanism provides a powerful yet simple user interface. Its implementation using horizontal strips is efficient in both time and space. To handle large circuits efficiently, Caesar repres... View full abstract»

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  • An Approach to Topological Pin Assignment

    Publication Year: 1984, Page(s):250 - 255
    Cited by:  Papers (30)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    One of the methods of increasing routability of an integrated circuit or printed circuit board, is to improve the assignment of connection nets to component (gate, chip, etc.) pins. The quality of a pin assignment is judged based on factors such as predicted wire length, wiring crossovers, and wiring congestion. This paper describes topological heuristic algorithms for pin assignment. Two stages, ... View full abstract»

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  • Correction to "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications"

    Publication Year: 1984, Page(s): 256
    Request permission for commercial reuse | PDF file iconPDF (50 KB)
    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu