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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 2 • April 1984

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Displaying Results 1 - 7 of 7
  • A CAD-Oriented Analytical MOSFET Model for High-Accuracy Applications

    Publication Year: 1984, Page(s):117 - 122
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    Explicit and accurate formulations for the surface potential against quasi-Fermi potential of the minority carriers in a long-channel MOS transistor are found. Moreover, it is shown that, for a variety of process parameters, these simple formulations, together with a suitable rearrangement of the Brews' model, can be fruitfully adopted for an accurate modeling of the MOST characteristics in all th... View full abstract»

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  • Characterizing the LSI Yield Equation from Wafer Test Data

    Publication Year: 1984, Page(s):123 - 126
    Cited by:  Papers (52)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    The results of production test on LSI wafers are analyzed to determine the parameters of the yield equation. Recognizing that a physical defect on a chip can produce several logical faults, the number of faults per defect is assumed to be a random variable with Poisson distribution. The analysis provides a relationship between the yield of the tested fraction of the chip area and the cumulative fa... View full abstract»

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  • Chip Substrate Resistance Modeling Technique for Integrated Circuit Design

    Publication Year: 1984, Page(s):126 - 134
    Cited by:  Papers (61)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1192 KB)

    With the advent of VLSI and the use of statistical simulation techniques to perform integrated circuit design, modeling of chip substrate resistance is becoming increasingly important to successful chip design. This paper will present a substrate resistance modeling technique which may be applied to the design of both FET and bipolar chips. After briefly presenting the theory behind the technique,... View full abstract»

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  • A Network Comparison Algorithm for Layout Verification of Integrated Circuits

    Publication Year: 1984, Page(s):135 - 141
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (936 KB)

    An algorithm is presented which compares the actual topology of an integrated circuit derived from its layout with a user-supplied description of the intended nominal circuit at the transistor level. Devices and nets in both circuits may be named arbitrarily. Using information about device types and pin types to weight the nodes of the corresponding graphs, isomorphism is tested and the names of d... View full abstract»

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  • PART: Programmable Array Testing Based on a Partitioning Algorithm

    Publication Year: 1984, Page(s):142 - 149
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1000 KB)

    PART is a system for PLA testing and design verification, intended to be properly interfaced with other existing tools to generate a comprehensive design environment. To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout information. PART aims at producing a very compact test set for all detectable crosspoint defects, us... View full abstract»

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  • Quantitative Evaluation of Self-Checking Circuits

    Publication Year: 1984, Page(s):150 - 155
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    Quantitative measures of self-checking power are defined for evaluation, comparison, and design of self-checking circuits. The self-testing and fault-secure properties have the corresponding quantitative measures testing input fraction (TIF), and secure input fraction (SIF). Averaging these measures over the fault set yields basic figures of merit. These simple averages can conceal faults with low... View full abstract»

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  • Three-Layer Channel Routing

    Publication Year: 1984, Page(s):156 - 163
    Cited by:  Papers (72)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB)

    With the advent of VLSI technology, multiple-layer routing becomes feasible. Two special types of three-layer channel routing, VHV and HVH, are introduced in this paper. The merging algorithm and the left edge algorithm used in two-layer routing can be extended to three layers. Attempts are made to compare the lower bounds of channel width of three types of routing--two-layer, VHV, and HVH. The al... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu