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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • October 1983

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Displaying Results 1 - 12 of 12
  • Editorial: Routing in Microelectronics

    Publication Year: 1983, Page(s):213 - 214
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

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  • Global Wiring by Simulated Annealing

    Publication Year: 1983, Page(s):215 - 222
    Cited by:  Papers (141)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1288 KB)

    Simulated annealing, a new general-purpose method of multivariate optimization, is applied to global wire routing for both idealized (synthetic) and actual designs of realistic size and complexity. Since the simulated annealing results are better than those obtained by conventional methods we use them as a standard against which to compare several sequential or greedy strategies commonly employed ... View full abstract»

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  • Hierarchical Wire Routing

    Publication Year: 1983, Page(s):223 - 234
    Cited by:  Papers (169)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1432 KB)

    We propose a new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels. Popularity of gate arrays technologies still remains high among VLSI chip manufacturers and, as the scale of integration grows, the interconnection problem becomes increasingly difficult if not intractable. The same is tr... View full abstract»

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  • Minimum-Via Topological Routing

    Publication Year: 1983, Page(s):235 - 246
    Cited by:  Papers (58)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1752 KB)

    A new approach to the two-dimensional routing utilizing two layers is proposed. It consists of two major steps, topological routing and geometrical mapping. This paper describes the topological routing algorithm in detail. Based on a circle graph representation of the net intersection information of the routing problem, a maximal set of nets that can be routed without vias are selected. The layer ... View full abstract»

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  • Single-Layer Routing for VLSI: Analysis and Algorithms

    Publication Year: 1983, Page(s):246 - 259
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2016 KB)

    In this paper we present a discussion of planarity testing and detailed single-layer routing. A program which implements the proposed algorithms for routing nets inside an arbitrarily shaped region has been written and tested. The results from this program are shown as examples. View full abstract»

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  • Efficient Single-Layer Routing Along a Line of Points

    Publication Year: 1983, Page(s):259 - 266
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1328 KB)

    In this paper we present several new procedures for carrying out the track assignment phase involved in channel routing. Our procedures are based upon the concept of an access graph which provides information dealing with the availability of routing space between pins in a layout. Paths for signal nets are then found by searching for optimal paths in the access graph. These paths can then be easil... View full abstract»

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  • A Rerouting Scheme for Single-Layer Printed Wiring Boards

    Publication Year: 1983, Page(s):267 - 271
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    A rerouting scheme is described, which is incorporated into an existing automatic routing system for single-layer printed wiring boards (PWB's) and hybrid integrated circuits. This scheme is to strip and reroute portions of the current wire patterns so that not only incomplete from-to's can be interconnected by means of getting rid of blockages, but those conductor paths so far determined which fo... View full abstract»

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  • Automatic Variable-Width Routing for VLSI

    Publication Year: 1983, Page(s):271 - 284
    Cited by:  Papers (11)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2000 KB)

    Some of the essentials for layout of complex VLSI circuits are hierarchical design based on macrocells of arbitrary size and shape, power nets with local varying width, signal nets with individual width and very compacted layouts which still have to guarantee all geometrical design rules. This paper is devoted to the problem of automatic routing with real geometries. VWROUT, a Variable Width Routi... View full abstract»

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  • An Automatic Routing Scheme for General Cell LSI

    Publication Year: 1983, Page(s):285 - 292
    Cited by:  Papers (27)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1056 KB)

    An automatic routing scheme intended dedicatedly for general cell LSI is described, which is constructed of a number of algorithms such as for net ordering, global routing, and detailed routing. This scheme is distinctive in that channel constraint loops are broken automatically at the stage of global routing, and a grid-free routing scheme is employed at the state of detailed routing. The routing... View full abstract»

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  • Order of Channels for Safe Routing and Optimal Compaction of Routing Area

    Publication Year: 1983, Page(s):293 - 300
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1128 KB)

    For a given placement of blocks and global routing of nets, a new formulation and its solution of the problem of determining the order of channels for the complete channel routing are presented. If the order of channels satisfying the condition exists, it is called the safe order since following it, each channel can be routed the wiring requirement without any prediction of necessary width. Thus t... View full abstract»

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  • Routing Techniques for Gate Array

    Publication Year: 1983, Page(s):301 - 312
    Cited by:  Papers (59)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1792 KB)

    This paper describes the routing techniques used for a Hughes internally developed high-density silicon-gate bulk CMOS gate array family. This layout software can be easily adapted to different array sizes and/or technologies (e.g., bipolar) through a change of parameters. A routing model and hierarchical decomposition schemes are presented to address the routability issue. More specifically, this... View full abstract»

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  • A New Global Router for Gate Array LSIsi

    Publication Year: 1983, Page(s):313 - 321
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1392 KB)

    A global router for gate array LSI's is described, which is intended to perform an interaction between placement and routing such that the features of one may be incorporated into those of another. This router is to generate for each net an interconnection pattern of channel segments in such a unified way of taking all interrelated interconnection requirements into account at once. A main objectiv... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu