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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 4 • Date October 1983

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Displaying Results 1 - 12 of 12
  • Editorial: Routing in Microelectronics

    Publication Year: 1983 , Page(s): 213 - 214
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

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  • Global Wiring by Simulated Annealing

    Publication Year: 1983 , Page(s): 215 - 222
    Cited by:  Papers (70)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1288 KB)  

    Simulated annealing, a new general-purpose method of multivariate optimization, is applied to global wire routing for both idealized (synthetic) and actual designs of realistic size and complexity. Since the simulated annealing results are better than those obtained by conventional methods we use them as a standard against which to compare several sequential or greedy strategies commonly employed in automatic wiring programs. View full abstract»

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  • Hierarchical Wire Routing

    Publication Year: 1983 , Page(s): 223 - 234
    Cited by:  Papers (127)  |  Patents (4)
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    We propose a new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels. Popularity of gate arrays technologies still remains high among VLSI chip manufacturers and, as the scale of integration grows, the interconnection problem becomes increasingly difficult if not intractable. The same is true for problems of switchbox and channel routing, which usually arise in custom designs; the uniformity of wiring substrate unites them with gate array routing problem. Our approach was initially aimed at gate arrays, but it extends naturally to switchboxes and channels. Uniformity of the wiring substrate is the crucial assumption of the method. It assumes that horizontal and vertical wire segments are realized on different wiring layers and vias are introduced each time a wire changes direction. Any "jogs" ("wrong way" wires) are prohibited. Within these limitations our approach is advantageous over the existing wiring methodologies. Our final layout of wires is independent of both net ordering and ordering of pins within the nets. The wire densities we are able to achieve are often higher than those achieved by other routers. Because of the hierarchical nature of our method it is inherently fast, usually by an order of magnitude faster than the routers based on wave propagation (maze running) technique. View full abstract»

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  • Minimum-Via Topological Routing

    Publication Year: 1983 , Page(s): 235 - 246
    Cited by:  Papers (55)  |  Patents (1)
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    A new approach to the two-dimensional routing utilizing two layers is proposed. It consists of two major steps, topological routing and geometrical mapping. This paper describes the topological routing algorithm in detail. Based on a circle graph representation of the net intersection information of the routing problem, a maximal set of nets that can be routed without vias are selected. The layer assignments for the selected nets are determined by a global analysis so that the total number of vias needed is minimum. The layer assignment problem turns out to be a maximum-cut problem on an edge-weighted graph and we developed a greedy algorithm for it. According to the layer assignments, the detailed topological routes are then generated. View full abstract»

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  • Single-Layer Routing for VLSI: Analysis and Algorithms

    Publication Year: 1983 , Page(s): 246 - 259
    Cited by:  Papers (16)
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    In this paper we present a discussion of planarity testing and detailed single-layer routing. A program which implements the proposed algorithms for routing nets inside an arbitrarily shaped region has been written and tested. The results from this program are shown as examples. View full abstract»

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  • Efficient Single-Layer Routing Along a Line of Points

    Publication Year: 1983 , Page(s): 259 - 266
    Cited by:  Papers (2)
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    In this paper we present several new procedures for carrying out the track assignment phase involved in channel routing. Our procedures are based upon the concept of an access graph which provides information dealing with the availability of routing space between pins in a layout. Paths for signal nets are then found by searching for optimal paths in the access graph. These paths can then be easily mapped back into routed wire segments on a VLSI chip. We consider only the case of single-layer routing within a single channel. We allow for wires to be on both sides of the line of pins to be processed, as well as between the pins. We consider two models, the first where the track availability is infinite, or equivalently, where wires are infinitely thin. We then consider the more realistic case where the track density in the channel is fixed. Our procedure for this case, called floating-track assignment, allows a wire, once assigned to a track, to be reassigned to a different track in order to enhance routability. For this case, we consider three objective functions, namely, minimal wire length, minimal congestion, and minimal perturbation. Both theoretical and experimental results are presented. View full abstract»

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  • A Rerouting Scheme for Single-Layer Printed Wiring Boards

    Publication Year: 1983 , Page(s): 267 - 271
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    A rerouting scheme is described, which is incorporated into an existing automatic routing system for single-layer printed wiring boards (PWB's) and hybrid integrated circuits. This scheme is to strip and reroute portions of the current wire patterns so that not only incomplete from-to's can be interconnected by means of getting rid of blockages, but those conductor paths so far determined which form unnecessarily long detours can be improved. Several implementation results are also shown. View full abstract»

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  • Automatic Variable-Width Routing for VLSI

    Publication Year: 1983 , Page(s): 271 - 284
    Cited by:  Papers (7)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2000 KB)  

    Some of the essentials for layout of complex VLSI circuits are hierarchical design based on macrocells of arbitrary size and shape, power nets with local varying width, signal nets with individual width and very compacted layouts which still have to guarantee all geometrical design rules. This paper is devoted to the problem of automatic routing with real geometries. VWROUT, a Variable Width Routing System is presented. This includes planar power net routing with variable width on a single layer, loose and final routing of signal nets with variable width on two layers (H-V routing), and layout compaction with design-rule verification. Though automatic routing systems have been developed successfully, the intention of this paper is to demonstrate that layout programs of today have not yet become perfect. A lot of effort in software development is necessary in order that automatic layouts can compared with manual designs. View full abstract»

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  • An Automatic Routing Scheme for General Cell LSI

    Publication Year: 1983 , Page(s): 285 - 292
    Cited by:  Papers (27)  |  Patents (2)
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    An automatic routing scheme intended dedicatedly for general cell LSI is described, which is constructed of a number of algorithms such as for net ordering, global routing, and detailed routing. This scheme is distinctive in that channel constraint loops are broken automatically at the stage of global routing, and a grid-free routing scheme is employed at the state of detailed routing. The routing program based on this scheme has been incorporated into a design system for LSI which is at work in practice. A part of implementation results are also shown. View full abstract»

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  • Order of Channels for Safe Routing and Optimal Compaction of Routing Area

    Publication Year: 1983 , Page(s): 293 - 300
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1128 KB)  

    For a given placement of blocks and global routing of nets, a new formulation and its solution of the problem of determining the order of channels for the complete channel routing are presented. If the order of channels satisfying the condition exists, it is called the safe order since following it, each channel can be routed the wiring requirement without any prediction of necessary width. Thus the compaction of the routing area can be made utmost each time. The idea is based on the general feature of channel routers not on any particular one. Related subjects such as the simultaneously routable channels, generalization of the safe order, switch box routing, and the placement with nonrectangular blocks are discussed. View full abstract»

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  • Routing Techniques for Gate Array

    Publication Year: 1983 , Page(s): 301 - 312
    Cited by:  Papers (42)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1792 KB)  

    This paper describes the routing techniques used for a Hughes internally developed high-density silicon-gate bulk CMOS gate array family. This layout software can be easily adapted to different array sizes and/or technologies (e.g., bipolar) through a change of parameters. A routing model and hierarchical decomposition schemes are presented to address the routability issue. More specifically, this paper focuses on the formulation and analysis of global routing and vertical assignment problems and gives a systematic breakdown of the routing task into well-defined subtasks. Instead of performing sequential routing, techniques and formulations are introduced to achieve a high degree of order independency in all subtasks. In routing subtasks where iterations are required, independent selection and interconnection are performed to avoid order dependency in typical routing problems. Implementation results are provided to indicate the efficiency of the system. View full abstract»

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  • A New Global Router for Gate Array LSIsi

    Publication Year: 1983 , Page(s): 313 - 321
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1392 KB)  

    A global router for gate array LSI's is described, which is intended to perform an interaction between placement and routing such that the features of one may be incorporated into those of another. This router is to generate for each net an interconnection pattern of channel segments in such a unified way of taking all interrelated interconnection requirements into account at once. A main objective of the router is not only to minimize the maximum of the local routing densities but also to distribute all the wiring requirements over channels evenly, in order to attain 100-percent interconnections within a limited area. An implementation result of the router is also shown. View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu