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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 2 • April 1983

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Displaying Results 1 - 9 of 9
  • Edisim: A Graphical Simulator Interface for LSI Design

    Publication Year: 1983, Page(s):57 - 61
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    A new CAD tool has been developed that provides the ability to interact graphically with the simulation of an LSI circuit. The tool is called EDISIM, for EDItor plus SIMulator. Compared with the textual interface provided by most simulators, the graphic interface of edisim is simpler to learn and faster to use for both the novice and the experienced designer. EDISIM displays the layout of a chip o... View full abstract»

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  • An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints

    Publication Year: 1983, Page(s):62 - 69
    Cited by:  Papers (60)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1256 KB)

    A popular algorithm to compact VLSI symbolic layout is to use a graph algorithm similar to finding the "longest path" in a network. The algorithm assumes that the spacing constraints on the mask elements are of the lower bound type. However, to enable the user to have close control over the compaction result, a desired symbolic layout system should allow the user to add either the equality or the ... View full abstract»

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  • A New Automatic Logic Interconnection Verification System for VLSI Design

    Publication Year: 1983, Page(s):70 - 82
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1776 KB)

    A new VLSI checking program, LIVES (Logic Interconnection VErification System), has been developed. LIVES verifies the geometrical layout data to determine whether or not it correctly reflects the original logic level description. An excellent LIVES feature, which no other programs have possessed yet, is that it can perform the check even when there are no identification marks on each logic gate i... View full abstract»

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  • A Logic Simulation Machine

    Publication Year: 1983, Page(s):82 - 94
    Cited by:  Papers (23)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2216 KB)

    Special-purpose CAD hardware is increasingly being considered as a means to meet the challenge posed to conventional (software-based) CAD tools by the growing complexity of VLSI circuits. In this paper we describe the architecture of a logic simulation machine employing distributed and parallel processing. Our architecture can accommodate different levels of modeling ranging from simple gates to c... View full abstract»

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  • Automating Technology Relative Logic Synthesis and Module Selection

    Publication Year: 1983, Page(s):94 - 105
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1880 KB)

    This paper discusses a design aid which translates the data part of a functional level digital design into a logic level design through the specification of module set information. The constraint driven automatic methodology is discussed and results of using the design aid are presented. Predictors are developed to estimate the logic level design space, thus providing early feedback within the des... View full abstract»

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  • A Simulation Model for Schottky Diodes in GaAs Integrated Circuits

    Publication Year: 1983, Page(s):106 - 111
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    A circuit simulation model for Schottky-barrier diodes is presented which accurately reproduces the diode's forward I-V characteristics. This is achieved by the inclusion of the nonlinear (current-dependent) series resistance typically observed in planar Schottky-barrier diodes. The diode model is targeted for large-signal transient and dc bias analysis where precise solutions are required. Notewo... View full abstract»

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  • An Efficient Numerical Algorithm for Simulation of MOS Capacitance

    Publication Year: 1983, Page(s):111 - 116
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    A new, computationally efficient method for the numerical evaluation of the equilibrium capacitance of one-dimensional MOS structures is presented. Capacitance-voltage (C-V) characteristics for arbitary impurity profiles and interface state distributions can be calculated for temperatures ranging from 50 K to 350 K. Examples of simulated C-V characteristics demonstrate the capability of the comput... View full abstract»

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  • Logic Partitioning for Minimizing Gate Arrays

    Publication Year: 1983, Page(s):117 - 121
    Cited by:  Papers (4)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    This paper describes a procedure for partitioning logic to minimize the number of gate arrays required to implement the logic. The procedure consists of three algorithms to perform initial, iterative, and interactive logic partitioning. Results are presented using three different logic circuits ranging in size from 14 000 gates to 26 000 gates. View full abstract»

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  • Table Look-Up MOSFET Modeling System Using a 2-D Device Simulator and Monotonic Piecewise Cubic Interpolation

    Publication Year: 1983, Page(s):121 - 126
    Cited by:  Papers (33)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    This paper describes a method for connecting an MOSFET 2-D device simulator to a circuit simulator via a 3-D table look-up MOSFET model. The computational cost of the device simulator is drastically reduced by a proposed monotonic piecewise cubic interpolation technique. With this technique, the device simulator needs to calculate only 100 ~ 200 points to make up an accurate 3-D table look-up MOSF... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu