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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 1 • Date January 1983

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Displaying Results 1 - 7 of 7
  • Editorial

    Page(s): 1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (79 KB)  

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  • Channel Length Dependence of the Body-Factor Effect in NMOS Devices

    Page(s): 2 - 4
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    The dependence of threshold voltage on substrate bias in NMOS devices is reevaluated in the light of a large sample of data for short-channel length devices (0.8 ?m < L < 8 ?m). Existing models [1], [2] do not fit the data with the necessary accuracy for circuit simulation of short channel devices. A new model involving only process parameters is presented which may also be used to evaluate xj and Nsub from a limited amount of observations if long channel devices are not available. Agreement with SUPREM is excellent. View full abstract»

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  • A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic

    Page(s): 4 - 18
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    This paper describes a method for formally modeling digital logic using algebraic relations. The relations model digital logic at the register-transfer (RT) level. An RT-level behaviorial specification is used to develop the relations, which express timing relationships that must be satisfied by any correct implementation. An extension of the model is shown which can be used for synthesis at the RT level. The growth rate and computational properties of the model are discussed, and an example of synthesis is shown. View full abstract»

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  • Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design

    Page(s): 18 - 29
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    BELLMAC-32A is a single-chip fully 32-bit high-end microprocessor designed in 2.5-?m twin-tub CMOS technology. This paper describes the gate matrix layout of random control logic in BELLMAC-32A with top-down hierarchical design methodology. The gate matrix layout provided (1) parallel team layout efforts, (2) adaptability to evolving logic design with short turnaround time, (3) high packing density competitive with hand layout, (4) compatibility with computer-aided layout and verification tools, (5) capability to fine-tune circuits, and (6) technology updatability. It took 6.5 engineer-years to complete the layout of random control logic with 7000 transistors although the logic design was continuously evolving during the layout period. The average packing density of gate matrix layout was 1500 ?m2 per transistor in random logic and 840 ?m2 per transistor in data path. BELLMAC-32A had more-than-three times performance improvement over its 3.5 ?m technology prototype chip BELLMAC-32, in which random control logic was implemented with polycells. View full abstract»

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  • On the Layering Problem of Multilayer PWB Wiring

    Page(s): 30 - 38
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    This paper deals with the layering problem of multilayer PWB wiring, associated with single-row routing. The problem to be considered is restricted to the special case of street capacities up to two in each layer, and it is reduced to a problem of the interval graph by relaxing some restrictions in the original problem. Then, a heuristic algorithm is proposed for this problem. View full abstract»

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  • A Parallel Processing Approach for Logic Module Placement

    Page(s): 39 - 47
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    A parallel processing algorithm for logic module placement is presented. Conventionally, such placement problems have been solved on a single processor in a sequential manner. In this paper, it is shown that a two-dimensional processor array structure can be applied to the placement problem, resulting in a substantial reduction of the processing time. This parallel processing algorithm is based on the concept that the adjacent pairwise exchange method could be expanded to the parallel processing case. By using simulation programs, it is shown that the placement results obtained by the parallel processing algorithm are a little better than those obtained by the sequential algorithm. In addition, the theoretical estimations in respect to the processing cycle iterations correspond well with the simulation results. View full abstract»

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  • A Simple Charge-Based Model for MOS Transistor Capacitances: A New Production Tool

    Page(s): 48 - 51
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    A new charge based MOS transistor model for capacitances which will conserve transient charges is introduced. The model is required to accurately simulate a certain class of dynamic circuits. This model features continuous charge formulation in all regions of operation: accumulation, cutoff, and strong inversion. Capacitances are continuous in all regions except on the strong inversion to cutoff border. The channel potential is approximated by novel and weighted functions of the drain and source potentials. A hyperbolic tangent function splits the channel charge in strong inversion between the source and drain. Charge conservation and accuracy of the model are demonstrated with some real examples. View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu