Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
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Issue 1 • Date January 1983
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Filter Results
Displaying Results 1 - 7 of 7
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A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic
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PDF (2320 KB)
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Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design
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PDF (2120 KB)
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On the Layering Problem of Multilayer PWB Wiring
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PDF (1592 KB)
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Aims & Scope
Contains articles on methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities.
Meet Our Editors
Editor-in-Chief
Sachin Sapatnekar
University of Minnesota
Dept. of Electrical and Computer Engineering
4-174 Keller Hall, 200 Union Street SE
Minneapolis, MN 55455 55455 USA
sachin@umn.edu
