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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 3 • Date March 2004

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Displaying Results 1 - 17 of 17
  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Optimal design of clock trees for multigigahertz applications

    Publication Year: 2004, Page(s):329 - 345
    Cited by:  Papers (9)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    With the onset of gigahertz frequencies on clocked digital systems, inductance effects become significant. We investigate appropriate regimes where signal propagation on an IC can be characterized as resulting from transmission line (TL) behavior. The signals propagate at a speed in the proximity of the speed of light in the medium. Our starting points are exact solutions in the time domain to the... View full abstract»

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  • Edge separability-based circuit clustering with application to multilevel circuit partitioning

    Publication Year: 2004, Page(s):346 - 357
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB) | HTML iconHTML

    In this paper, we propose a new efficient O(nlogn) connectivity-based bottom-up clustering algorithm called edge separability-based clustering (ESC). Unlike existing bottom-up algorithms that are based on local connectivity information of the netlist, ESC exploits more global connectivity information using edge separability to guide the clustering process, while carefully monitoring cluster area b... View full abstract»

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  • UTACO: a unified timing and congestion optimization algorithm for standard cell global routing

    Publication Year: 2004, Page(s):358 - 365
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    Timing performance and routability are two main goals of global routing. These two targets are mutually conflicting if we view and handle their effects independently. In this paper, we adopt a shadow price mechanism to incorporate the two issues into one unified objective function. We formulate global routing as a multicommodity flow problem. The objective function is the slack of congestion with ... View full abstract»

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  • Full-chip routing optimization with RLC crosstalk budgeting

    Publication Year: 2004, Page(s):366 - 377
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB) | HTML iconHTML

    Existing layout-optimization methods for both capacitive and inductive (RLC) crosstalk reduction assume a set of interconnects with a priori given crosstalk bounds in a routing region. RLC crosstalk budgeting is critical for effectively applying these methods at the full-chip level. In this paper, we formulate a full-chip routing optimization problem with RLC crosstalk budgeting, and solve this pr... View full abstract»

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  • 2-D CA variation with asymmetric neighborship for pseudorandom number generation

    Publication Year: 2004, Page(s):378 - 388
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB) | HTML iconHTML

    This paper proposes a variation of two-dimensional (2-D) cellular automata (CA) by adopting a simpler structure than the normal 2-D CA and a unique neighborship characteristic-asymmetric neighborship. The randomness of 2-D CA based on asymmetric neighborship is discussed and compared with one-dimensional (1-D) and 2-D CA. The results show that they are better than 1-D CA and could compete with con... View full abstract»

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  • An analytical integration method for the simulation of continuous-time ΔΣ modulators

    Publication Year: 2004, Page(s):389 - 399
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB) | HTML iconHTML

    Circuit-level simulation of ΔΣ modulators is a time-consuming task, taking one or more days for meaningful results. While there are a great variety of techniques and tools that speed up the simulations for discrete-time ΔΣ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous-time counterpart. Nevertheless, in t... View full abstract»

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  • The effects of unsymmetric matrix permutations and scalings in semiconductor device and circuit simulation

    Publication Year: 2004, Page(s):400 - 411
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB) | HTML iconHTML

    The solution of large sparse unsymmetric linear systems is a critical and challenging component of semiconductor device and circuit simulations. The time for a simulation is often dominated by this part. The sparse solver is expected to balance different, and often conflicting requirements. Reliability, a low memory-footprint, and a short solution time are a few of these demands. Currently, no bla... View full abstract»

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  • Simplifying Boolean constraint solving for random simulation-vector generation

    Publication Year: 2004, Page(s):412 - 420
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    Simulation by random vectors is meaningful only if the vectors meet certain requirements on the environment that drives the design under verification. When that environment is modeled by constraints, we face the problem of solving constraints efficiently. We present an efficient algorithm for simplifying conjunctive Boolean constraints defined over state and input variables, and apply it to constr... View full abstract»

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  • X-compact: an efficient response compaction technique

    Publication Year: 2004, Page(s):421 - 432
    Cited by:  Papers (140)  |  Patents (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    X-Compact is an X-tolerant test response compaction technique. It enables up to exponential reduction in the test response data volume and the number of pins required to collect test response from a chip. The compaction hardware requires negligible area, does not add any extra delay during normal operation, guarantees detection of defective chips even in the presence of unknown logic values (often... View full abstract»

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  • Extraction of two-node bridges from large industrial circuits

    Publication Year: 2004, Page(s):433 - 439
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    Enumeration and prioritization of highly probable bridges based on the circuit layout and manufacturing defect data is a key step in defect-based testing. Existing solutions either do not scale to large designs or compromise on the accuracy of the computation when applied to very large circuits. This paper presents a scalable and efficient methodology to accurately extract two-node bridges from ve... View full abstract»

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  • Synthesis of fully testable circuits from BDDs

    Publication Year: 2004, Page(s):440 - 443
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show... View full abstract»

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  • A delay metric for RC circuits based on the Weibull distribution

    Publication Year: 2004, Page(s):443 - 447
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (211 KB) | HTML iconHTML

    Physical synthesis optimizations require fast and accurate analysis of RC networks. Elmore first proposed matching circuit moments to a probability density function (PDF), which led to widespread adoption of his simple and fast metric. The more recently proposed PRIMO and H-gamma metrics match the circuit moments to the PDF of a Gamma statistical distribution. We instead propose to match the circu... View full abstract»

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  • 2004 IEEE Asia-Pacific Conference on Circuits and Systems

    Publication Year: 2004, Page(s): 448
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu