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Computers and Digital Techniques, IEE Proceedings -

Issue 1 • Date 15 Jan. 2004

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Displaying Results 1 - 10 of 10
  • Testing of stuck-open faults in generalised Reed-Muller and EXOR sum-of-products CMOS circuits

    Page(s): 83 - 91
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (463 KB)  

    Testable designs of GRM (generalised Reed-Muller) and ESOP (EXOR sum-of-products) circuits have been proposed for robustly detecting all single stuck-open faults in their CMOS implementation. It is shown that for an n-variable boolean function, a sequence of (4n + 13) vectors is sufficient to detect all single stuck-open faults in a GRM circuit. For an ESOP circuit, a test sequence of length (2n + 10) is sufficient. In the first case, the EXOR part is designed as a tree of depth ≤2(logp + 1 ), and for the latter, as a linear cascade of length ≤(p + 1), where p is the number of product terms in the GRM or ESOP expression. For both the cases the test sequence is universal, i.e. independent of the function and the circuit under test, and can be stored in a ROM for built-in self-test. View full abstract»

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  • Finite state machine state assignment targeting low power consumption

    Page(s): 61 - 70
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (322 KB)  

    The authors present a genetic-algorithm-based approach for finite state machine synthesis that targets low power consumption. The approach follows a partitioning strategy to ensure that the states with a high transition probability between themselves are encoded to have smaller Hamming distances. The approach shows significant power savings in both two- and multi-level realisations of the resulting circuitry. View full abstract»

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  • Low-power system-on-chip architecture for wireless LANs

    Page(s): 2 - 15
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1649 KB)  

    The authors present the architecture of a low-power system-on-chip (SoC) that implements baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. The design is based on the HIPERLAN/2 wireless LAN standard, but it also covers critical processing requirements of the IEEE 802.11a standard. The options, constraints and motivations for the taken design decisions are presented, and the followed design steps, starting from the system specifications up to the architecture definition and the system implementation, are explained. The system's functionality covers both mobile terminal and access point devices. A critical design task in such systems is the assignment of the target system's tasks on the different types of processing elements available. Processor cores, dedicated hardware as well as memory elements and advanced bus architectures are used in order to achieve the target implementation. The architecture is targeted for a low-power SoC platform, due to the fact that power consumption is a critical parameter in electronic portable system design where excess power dissipation can lead to expensive and less reliable systems. A system prototype has been developed on a FPGA-based platform (including microprocessor modules). This FPGA-based prototype is currently being migrated to a SoC, which requires that the treatment of important issues such as clock handling, synthesis, testability and debugging is addressed. View full abstract»

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  • Architectural probing: a new paradigm for enabling communication refinement in SOC design

    Page(s): 23 - 32
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    A system-level exploration method called architectural probing is proposed. It embodies the widely accepted concepts of behaviour/architecture codesign, and allows one to selectively gather functional information from a functional diagram and feed it into an architectural diagram, thus enabling a reduction in the amount of details that are simulated at the architectural level. The effectiveness of this method is demonstrated in a case study that involves the exploration of data queuing management schemes for a packet switch system. As shown in the experimental results, the method enables the evaluation of the impact of different data management algorithms and different system parameters such as DMA size and packet payload size, in terms of power and performance tradeoff by estimating the average energy-per-bit-transferred, on each architectural component, such as memories, buses and bus arbiters, involved in the implementation of the queuing management system. View full abstract»

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  • Data-adaptive motion estimation algorithm and VLSI architecture design for low-power video systems

    Page(s): 51 - 59
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (573 KB)  

    A data-adaptive video motion estimation algorithm and its low-power VLSI implementation are presented. The proposed technique exploits the input data variations to dynamically reconfigure the search-window size of an exhaustive block-matching search thus avoiding unnecessary computations and memory accesses. Both spatial and temporal correlations of the motion vector field are taken into account. A quality analysis based on several test conditions confirms the efficiency of the motion estimator when compared with the conventional full-search as well as other low-complexity motion-estimation techniques. Realised in 0.25 μm CMOS technology, it allows for the same high performance of the full-search approach while considerably reducing power consumption from 70 up to 90% for typical QCIF and CIF video sequences. View full abstract»

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  • Energy-efficient Java execution using local memory and object co-location

    Page(s): 33 - 42
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1005 KB)  

    With the paradigm shift in computer systems towards ubiquitous computing, energy, together with performance, has become an important parameter to measure efficiency. Java is increasingly becoming the programming language of choice for applications expected to run in embedded and mobile environments. Java's platform independence and security features serve very well the needs of these environments, which expect the same application to run in a variety of environments in a secure manner. The devices used in these environments, for example hand-held computers, have a limited battery life. The needs to increase the period between recharges and to decrease the cooling costs provide the incentive to incorporate energy as an important parameter. The authors propose two implementation strategies for allocating objects that can significantly reduce the memory system energy consumption of Java applications. The first strategy uses a part of the on-chip memory resources as a local memory to achieve better performance than a cache-only architecture. The object allocation strategy is implemented using an annotation-based approach and shown to be effective in improving performance and reducing the memory system energy consumption. Specifically, energy consumption is reduced by up to 39% and cache miss rate by up to 31%. The second strategy is object co-location, which exploits the temporal locality already present in heap references to achieve better spatial locality. The object co-location is implemented in the garbage collector of a Java virtual machine. This reduces the cache miss rate by up to 47%, and a subsequent reduction in the memory energy consumption by up to 49% is observed. View full abstract»

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  • Simultaneous routing and buffering in SOC floorplan design

    Page(s): 17 - 22
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (521 KB)  

    An EDA tool to deal with the problems of routing and buffer-insertion in system-on-chip floorplanning simultaneously is developed. This routing and buffering tool mainly consists of a Manhattan routing (MR) algorithm and a maze-based between-buffer routing algorithm. Since the processing speed of its MR is very fast, this tool can be integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution. View full abstract»

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  • dMT: inexpensive throughput enhancement in small-scale embedded microprocessors with differential multithreading

    Page(s): 43 - 50
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    The authors examine differential multithreading (dMT) as an attractive organisation for increasing throughput in simple, small-scale, pipelined processors like those used in embedded environments. dMT copes with pipeline stalls due to hazards and data- and instruction-cache misses by using duplicated pipeline registers to run instructions from an alternate thread. Results show that dMT boosts throughput substantially and can in fact replace dynamic branch prediction or can be used to reduce the sizes of the instruction and data caches. View full abstract»

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  • Formal verification of a SONET data stream processor

    Page(s): 71 - 81
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1038 KB)  

    We describe the formal verification of an industrial hardware design from PMC-Sierra, Inc. The design under investigation is a telecom system block, which processes a portion of the synchronous optical network (SONET) line overhead of a received data stream. We adopted a hierarchical modelling and verification approach which follows the natural design hierarchy. The formal specification and verification have been carried out based on multiway decision graphs (MDG), a new decision diagram subsuming the traditional binary decision diagrams and allowing abstract data and functions. The verification has been performed using both equivalence and model checking. To measure the performance of the MDG-based model checking, we also conducted a comparative verification of the same design using Cadence FormalCheck. View full abstract»

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