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Micro, IEEE

Issue 1 • Date Jan.-Feb. 2004

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Displaying Results 1 - 18 of 18
  • IEEE micro

    Page(s): 0_1
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  • Micro Review - Single sourcing mount fuji

    Page(s): 74 - 75
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    Freely Available from IEEE
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  • Architecture for a hardware-based, TCP/IP content-processing system

    Page(s): 62 - 69
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    The transmission control protocol is the workhorse protocol of the Internet. Most of the data passing through the Internet transits the network using TCP layered atop the Internet protocol (IP). Monitoring, capturing, filtering, and blocking traffic on high-speed Internet links requires the ability to directly process TCP packets in hardware. High-speed network intrusion detection and prevention systems guard against several types of threats. As the gap between network bandwidth and computing power widens, improved microelectronic architectures are needed to monitor and filter network traffic without limiting throughput. To address these issues, we've designed a hardware-based TCP/IP content-processing system that supports content scanning and flow blocking for millions of flows at gigabit line rates. The TCP splitter2 technology was previously developed to monitor TCP data streams, sending a consistent byte stream of data to a client application for every TCP data flow passing through the circuit. The content-scanning engine can scan the payload of packets for a set of regular expressions. The new TCP-based content-scanning engine integrates and extends the capabilities of the TCP splitter and the old content-scanning engine. IP packets travel to the TCP processing engine from the lower-layer-protocol wrappers. Hash tables are used to index memory that stores each flow's state. View full abstract»

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  • IEEE micro - staff list

    Page(s): 4
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  • IEEE Computer Society Information

    Page(s): 70
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  • Deep packet inspection using parallel bloom filters

    Page(s): 52 - 61
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    There is a class of packet processing applications that inspect packets deeper than the protocol headers to analyze content. For instance, network security applications must drop packets containing certain malicious Internet worms or computer viruses carried in a packet payload. Content forwarding applications look at the hypertext transport protocol headers and distribute the requests among the servers for load balancing. Packet inspection applications, when deployed at router ports, must operate at wire speeds. With networking speeds doubling every year, it is becoming increasingly difficult for software-based packet monitors to keep up with the line rates. We describe a hardware-based technique using Bloom filters, which can detect strings in streaming data without degrading network throughput. A Bloom filter is a data structure that stores a set of signatures compactly by computing multiple hash functions on each member of the set. This technique queries a database of strings to check for the membership of a particular string. The answer to this query can be false positive but never a false negative. An important property of this data structure is that the computation time involved in performing the query is independent of the number of strings in the database provided the memory used by the data structure scales linearly with the number of strings stored in it. Furthermore, the amount of storage required by the Bloom filter for each string is independent of its length. View full abstract»

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  • End-to-end performance of 10-gigabit Ethernet on commodity systems

    Page(s): 10 - 22
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    Apart form the success in local-area networks (LANs) and system-area networks and anticipated success in metropolitan and wide area networks (MANs and WANs), Ethernet continues to evolve to meet the increasing demands of packet-switched networks. Although the recently ratified 10-Gigabit Ethernet standard differs from earlier Ethernet standards, primarily in that 10GbE operates only over fiber and only in full-duplex mode, the differences are largely superficial. More importantly, l0GbE does not make obsolete current investments in network infrastructure. The 10GbE standard ensures interoperability not only with existing Ethernet but also with other networking technologies such as Sonet, thus paving the way for Ethernets expanded use in MANs and WANs. The world's first host-based 10GbE adapter, officially known as the Intel PRO/10GbE LR server adapter, introduces the benefits of l0GbE connectivity into LAN and system-area network environments, thereby accommodating the growing number of large-scale cluster systems and bandwidth-intensive applications, such as imaging and data mirroring. The 10GbE controller is optimized for servers that use the I/O bus backplanes of the peripheral component interface (PCI) and its higher speed extension, PCI-X. View full abstract»

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  • Asynchronous interconnect for synchronous SoC design

    Page(s): 32 - 41
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    System-on-chip (SoC) designs integrate a variety of cores and I/O interfaces, which usually operate at different clock frequencies. Communication between unlocked clock domains requires careful synchronization, which inevitably introduces metastability and some uncertainty in timing. Thus, any chip with multiple clock domains is already globally asynchronous. We have devised a more elegant and efficient solution to the multiple-clock-domain problem. Instead of gluing synchronous domains directly to each other with clock-domain bridges, we use asynchronous-circuit design techniques to handle all clock-domain crossing as well as all cross-chip communication and routing. The phase-locked loop (PLL) and clock distribution can be entirely local to each synchronous core, easing timing closure and improving the reusability of cores across multiple designs. Our solution, Nexus, is a globally asynchronous, locally synchronous (GALS) interconnect that features a 16-port, 36-bit asynchronous crossbar. The crossbar connects through asynchronous channels to clock-domain converters for each synchronous module. To ensure that Nexus will work robustly in a commercial application, we developed and applied many verification and test strategies, including novel variations of noise analysis, timing analysis, and fault and delay testing. View full abstract»

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  • Microbenchmark performance comparison of high-speed cluster interconnects

    Page(s): 42 - 51
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    Today's distributed and high-performance applications require high computational power and high communication performance. Recently, the computational power of commodity PCs has doubled about every 18 months. At the same time, network interconnects that provide very low latency and very high bandwidth are also emerging. This is a promising trend in building high-performance computing environments by clustering - combining the computational power of commodity PCs with the communication performance of high-speed network interconnects. There are several network interconnects that provide low latency and high bandwidth. Traditionally, researchers have used simple microbenchmarks, such as latency and bandwidth tests, to characterize a network interconnects communication performance. Later, they proposed more sophisticated models such as LogP. However, these tests and models focus on general parallel computing systems and do not address many features present in these emerging commercial interconnects. Another way to evaluate different network interconnects is to use real-world applications. However, real applications usually run on top of a middleware layer such as the message passing interface (MPI). Our results show that to gain more insight into the performance characteristics of these interconnects, it is important to go beyond simple tests such as those for latency and bandwidth. In future, we plan to expand our microbenchmark suite to include more tests and more interconnects. View full abstract»

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  • ETA: experience with an Intel Xeon processor as a packet processing engine

    Page(s): 24 - 31
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    Server-based networks have well-documented performance limitations. These limitations outline a major goal of Intel's embedded transport acceleration (ETA) project, the ability to deliver high-performance server communication and I/O over standard Ethernet and transmission control protocol/Internet protocol (TCP/IP) networks. By developing this capability, Intel hopes to take advantage of the large knowledge base and ubiquity of these standard technologies. With the advent of 10 gigabit Ethernet, these standards promise to provide the bandwidth required of the most demanding server applications. We use the term packet processing engine (PPE) as a generic term for the computing and memory resources necessary for communication-centric processing. Such PPEs have certain desirable attributes; the ETA project focuses on developing PPEs with such attributes, which include scalability, extensibility, and programmability. General-purpose processors, such as the Intel Xeon in our prototype, are extensible and programmable by definition. Our results show that software partitioning can significantly increase the overall communication performance of a standard multiprocessor server. Specifically, partitioning the packet processing onto a dedicated set of compute resources allows for optimizations that are otherwise impossible when time sharing the same compute resources with the operating system and applications. View full abstract»

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  • Micro law

    Page(s): 7 - 73
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  • Micro news

    Page(s): 6
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  • Table of contents

    Page(s): 1 - 2
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  • Call for papers

    Page(s): 23
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  • Why inventors are not famous

    Page(s): 76 - 78
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School of Electrical and Computer Engineering
IBM T.J. Watson Research Center