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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 2 • Date Feb. 2004

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Guest Editorial

    Publication Year: 2004, Page(s):129 - 130
    Cited by:  Papers (1)
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  • Statistical analysis of subthreshold leakage current for VLSI circuits

    Publication Year: 2004, Page(s):131 - 139
    Cited by:  Papers (95)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (309 KB) | HTML iconHTML

    We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the lea... View full abstract»

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  • Leakage current reduction in CMOS VLSI circuits by input vector control

    Publication Year: 2004, Page(s):140 - 154
    Cited by:  Papers (115)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (551 KB) | HTML iconHTML

    The first part of this paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" signal is used to shift in a new set of external inputs and pre-selected internal signals into the ... View full abstract»

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  • Gate oxide leakage current analysis and reduction for VLSI circuits

    Publication Year: 2004, Page(s):155 - 166
    Cited by:  Papers (65)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (538 KB) | HTML iconHTML

    In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simpl... View full abstract»

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  • Circuit and microarchitectural techniques for reducing cache leakage power

    Publication Year: 2004, Page(s):167 - 184
    Cited by:  Papers (75)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1010 KB) | HTML iconHTML

    On-chip caches represent a sizable fraction of the total power consumption of microprocessors. As feature sizes shrink, the dominant component of this power consumption will be leakage. However, during a fixed period of time, the activity in a data cache is only centered on a small subset of the lines. This behavior can be exploited to cut the leakage power of large data caches by putting the cold... View full abstract»

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  • Level conversion for dual-supply systems

    Publication Year: 2004, Page(s):185 - 195
    Cited by:  Papers (65)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (609 KB) | HTML iconHTML

    Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. Additionally, circuit robustness against supply bounce is a key property that differentiates good level converter design. Novel fl... View full abstract»

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  • LECTOR: a technique for leakage reduction in CMOS circuits

    Publication Year: 2004, Page(s):196 - 205
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (593 KB) | HTML iconHTML

    In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed technique, we introduce two leakage control transi... View full abstract»

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  • The Chimaera reconfigurable functional unit

    Publication Year: 2004, Page(s):206 - 217
    Cited by:  Papers (61)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB) | HTML iconHTML

    By strictly separating reconfigurable logic from the host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper, we describe Chimaera, a system that overcomes the communication bottleneck by integrating reconfigurable logic into the host processor itself. With direct access to the host processor's register file, the system enables the creatio... View full abstract»

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  • High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme

    Publication Year: 2004, Page(s):218 - 226
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (663 KB) | HTML iconHTML

    Among existing works of high-speed pipelined adaptive decision feedback equalizer (ADFE), the pipelined ADFE using relaxed look-ahead technique results in a substantial hardware saving than the parallel processing or Look-ahead approaches. However, it suffers from both the signal-to-noise ratio (SNR) degradation and slow convergence rate. In this paper, we employ the predictive parallel branch sli... View full abstract»

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  • IEEE Computer Society Annual Symposium on VLSI

    Publication Year: 2004, Page(s): 227
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  • IEEE International Symposium on Circuits and Systems (ISCAS2004)

    Publication Year: 2004, Page(s): 228
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  • The 13th International Workshop on Logic & Synthesis (IWLS)

    Publication Year: 2004, Page(s): 229
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  • International Symposium on Low Power Electronics and Design (ISLPED'04)

    Publication Year: 2004, Page(s): 230
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  • IEEE Member Digital Library [advertisement]

    Publication Year: 2004, Page(s): 231
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  • Proceedings of the IEEE celebrating 92 years of in-depth coverage on emerging technologies

    Publication Year: 2004, Page(s): 232
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integrated (VLSI) Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu