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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb. 2004

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Displaying Results 1 - 15 of 15
  • Table of contents

    Publication Year: 2004 , Page(s): 01
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Publication Year: 2004 , Page(s): 0_2
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  • Changes in the Editorial Board

    Publication Year: 2004 , Page(s): 1
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  • Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction

    Publication Year: 2004 , Page(s): 2 - 11
    Cited by:  Papers (37)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB) |  | HTML iconHTML  

    The authors present a comprehensive characterization method applied to the study of the state-of-the-art 18-μm CMOS process. Statistical characterization of gate CD reveals a large spatial intrafield component, strongly dependent on the local layout patterns. The authors describe the statistical analysis of this data and demonstrate the need for such comprehensive characterization. They describe the experimental setup of the novel measurement-based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate circuit modeling and statistical design for increased performance and yield. Characterization is based upon an inexpensive electrically based measurement technique. A rigorous statistical analysis of the impact of intrafield variability on circuit performance is undertaken. They show that intrafield CD variation has a significant detrimental effect on the overall circuit performance that may be as high as 25%. Moreover, they demonstrate that the spatial component of gate CD variability, rather than the proximity-dependent component, is predominantly responsible for speed degradation. In order to reduce the degradation of circuit performance and yield, the authors propose a mask-level spatial gate CD correction algorithm to reduce the intrafield and overall variability and provide an analytical model to evaluate the effectiveness of correction for variance reduction. They believe that potentially significant benefits can be achieved through implementation of this compensation technique in the production environment. View full abstract»

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  • Extrusion spin coating: an efficient and deterministic photoresist coating method in microlithography

    Publication Year: 2004 , Page(s): 12 - 21
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    Extrusion spin coating was developed to reduce photoresist waste and to improve coating uniformity in microlithography. This new method uses an efficient extrusion coating technique to apply a thin film of resist to a wafer prior to spinning. This initial layer of photoresist eliminates the spreading phase, the most inefficient step in conventional spin coating. The initial layer also provides existing spin coating models with preset initial conditions, allowing the prediction of coating thickness and uniformity a priori. This paper compares the experimental results with Emslie et al.'s predictive models of spin coating. A solvent concentration of 80% or higher in the coating chamber environment was found to be necessary to attain a predictable coating thickness with 5-Å uniformity. With optimized process variables, the mean coating thickness matched theoretical predictions within a variation of 0.01 μm. Defect-free coating results were achieved with coating efficiencies as high as 40%. View full abstract»

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  • Time minimization for a three-step cyclic process of deposition and diffusion

    Publication Year: 2004 , Page(s): 22 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB) |  | HTML iconHTML  

    The optimal layer thickness for minimizing the total time to build a layer with a three-step cyclic process of deposition and diffusion, or "annealing," is determined. Deposition and diffusion processes scale rather differently according to time. This analysis, for the building of a TiN barrier layer, quantifies those times in a model and is then used to find the thickness that minimizes a total time function across more than one process. This model would apply equally to the doping of SiO2 strata. View full abstract»

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  • Noncontact critical dimension metrology sensor for chrome photomasks featuring a low-temperature co-fired ceramic technology

    Publication Year: 2004 , Page(s): 25 - 34
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1040 KB)  

    This paper describes a noncontact capacitive-sensor metrology sensor developed to measure minimum feature sizes, also called critical dimensions, patterned on photomasks that are used in semiconductor device manufacture. Additionally, this paper describes the test structures printed on photomasks that facilitate linewidth metrology with the new sensor. The metrology sensor is fabricated using a low temperature co-fired ceramic technology and its principle is based on noncontact microcapacitance measurements of features on chrome-on-glass reticles. View full abstract»

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  • Sensitive strain measurements of bonded SOI films using Moire´

    Publication Year: 2004 , Page(s): 35 - 41
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    The authors have developed a simple technique to quantify strain in bonded Si films and used it to compare the strain induced by two distinct wafer bonding methods. This method consists of patterning sets of moire´ gratings on silicon-on-insulator (SOI) substrates prior to bonding using a G-line stepper. After planarization, bonding, and etch-back, the same lithography step is performed on the flipped patterns. The resultant interference between upper and lower gratings produces moire´ fringes which is a measure of the strain. In the experiments, the sensitivity of the measurement is approximately 20 nm. This approach has been used to compare two methods of wafer bonding. The first method, a manual bonding technique, yielded strain of up to 100 nm/mm. The second method employed a commercial-grade bonder and resulted in film strains below 40 nm/mm. In the bonding schemes the authors have studied, they believe strain results mainly from induced wafer bow during bonding and stress contributions of deposited films. This scheme was developed to address wafer strain that arises from a direct-alignment double-gate MOSFET fabrication scheme (Meinhold, 1994). View full abstract»

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  • Deadlock-free scheduling of photolithography equipment in semiconductor fabrication

    Publication Year: 2004 , Page(s): 42 - 54
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB) |  | HTML iconHTML  

    This paper presents the development of an efficient approach to the deadlock-free scheduling of photolithography equipment in semiconductor fabrication. Trends toward high automation and flexibility in the photolithography equipment accelerate the necessity of an intelligent scheduler that can guarantee reliability and improve the productivity of the photolithography equipment. Therefore, the scheduler of the photolithography equipment should be able to handle failures of process modules and deadlock while optimizing its performance measures such as throughput and utilization. The contingency of failure of process modules makes the tasks of optimizing the performance measures and managing deadlock more difficult because failure of process modules can change states unexpectedly and deadlock situations can vary dynamically according to failure of process modules. This paper proposes a deadlock-free scheduling approach that can perform scheduling and deadlock management in an efficient way for photolithography equipment, in spite of failures of process modules. First, this paper presents a novel framework in which the authors decompose the deadlock management problem into subproblems and then integrate them with scheduling algorithms. In other words, they identify deadlock-prone and deadlock-safe process modules in the context of the deadlock management and then focus on the deadlock-prone process modules to guarantee deadlock-freeness when applying scheduling algorithms to all of the process modules. To realize the proposed framework, a resource request matrix is introduced to represent operational states. The resource request matrix provides an explicit representation of the deadlock situations, which is useful in identifying deadlock-prone process modules and applying deadlock management algorithms. The authors also present algorithms of polynomial complexity to identify deadlock-prone process modules and algorithms to manage deadlock, which take failures of process modules into consideration. View full abstract»

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  • Scrapping small lots in a low-yield and high-price scenario

    Publication Year: 2004 , Page(s): 55 - 67
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB) |  | HTML iconHTML  

    Some wafers in a lot may become spoiled after they are processed at a workstation; such a lot is called a small lot. In a low yield and high price scenario, scrapping small lots may increase revenue and profit; yet, this notion has seldom been examined. This study presents a model for formulating the decision-making problem of scrapping small lots. A genetic algorithm is used to solve the problem when the solution space is large. An exhaustive search method is used when the solution space is small. Some numerical examples are used to evaluate the outcome of scrapping small lots. The profit obtained by the proposed scrapping method may be up to 23% higher than that obtained without scrapping. View full abstract»

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  • An optimal residency-aware scheduling technique for cluster tools with buffer module

    Publication Year: 2004 , Page(s): 68 - 73
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    Cluster tools provide a flexible, reconfigurable, and efficient environment for several manufacturing processes (e.g., semiconductor manufacturing). A new timing constraint (distinct from a simple deadline), referred to as residency constraint, puts a timing limit on the time that a wafer can stay in a processing module in a cluster tool. The authors demonstrate that a solution that does not address residency constraints can be found easily. However, when residency constraints are added to the model, the problem becomes complex and a scheduling technique may spend a long time searching for a good solution. Also, in some cases, one may need to decrease throughput to satisfy residency constraints. The authors introduce a new technique to address cluster tool scheduling in the presence of residency constraints. The proposed technique uses a buffer resource for temporarily holding wafers to release other resources such as the robot arm. This resource is usually available in the tool for maintenance reasons. A tradeoff is discussed in using the buffer resource and a scheduling algorithm is presented that will use this resource when it can help to increase throughput under residency constraints. The experiments show that in many cases that are common in semiconductor manufacturing, use of their proposed technique can improve throughput. View full abstract»

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  • 2004 IEEE Compound Semiconductor IC Symposium call for papers

    Publication Year: 2004 , Page(s): 74
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  • IEEE copyright form

    Publication Year: 2004 , Page(s): 75 - 76
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  • IEEE Transactions on Semiconductor Manufacturing information for authors

    Publication Year: 2004 , Page(s): c3
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  • [Breaker page]

    Publication Year: 2004 , Page(s): c4
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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721