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Electron Device Letters, IEEE

Issue 1 • Date Jan. 2004

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Displaying Results 1 - 20 of 20
  • Table of contents

    Publication Year: 2004 , Page(s): 01
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  • IEEE Electron Device Letters Society Information

    Publication Year: 2004 , Page(s): 0_2
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  • Monte Carlo simulation of Schottky diodes operating under terahertz cyclostationary conditions

    Publication Year: 2004 , Page(s): 1 - 3
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB) |  | HTML iconHTML  

    We report Monte Carlo simulations of the current response and noise spectrum in heavily doped nanometric GaAs Schottky-barrier diodes (SBDs) operating under periodic large-signal conditions in the forward bias region. Due to the rather thin depletion region and heavy doping of these diodes, we find that the returning carrier resonance is shifted well above the terahertz region, so that the low-frequency noise plateau extends over the terahertz region. Here, frequency multiplication and mixing can take place at noise levels equal or below than that of full shot noise. We show that the signal-to-noise ratio of these SBDs is definitely superior to that of bulk semiconductors exploiting velocity-field nonlinearity. View full abstract»

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  • Bias and temperature dependence of Sb-based heterostructure millimeter-wave detectors with improved sensitivity

    Publication Year: 2004 , Page(s): 4 - 6
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (147 KB) |  | HTML iconHTML  

    Nearly lattice-matched InAs/AlSb/GaSb-based heterostructure backward diodes for zero-bias millimeter wave detection were fabricated and measured. A record-high curvature, /spl gamma/=39.1 V/sup -1/, at zero bias was measured. On-wafer sensitivity measurements from 1 to 110 GHz gave a record-high average sensitivity of 3687 V/W for zero-bias operation. Further enhancement of detector sensitivity was observed with applied dc bias, with a sensitivity of 7996 V/W obtained for a 0.9 μA bias. Extrapolating the conjugately-matched measured sensitivity suggests that 1000 V/W should be achievable at a record-high 541 GHz. The temperature dependence of detector sensitivity was evaluated from measured dc current-voltage characteristics and gave expected sensitivities ranging from 3910 V/W at 293 K to 7740 V/W at 4.2 K. View full abstract»

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  • High-power polarization-engineered GaN/AlGaN/GaN HEMTs without surface passivation

    Publication Year: 2004 , Page(s): 7 - 9
    Cited by:  Papers (37)  |  Patents (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB) |  | HTML iconHTML  

    In this paper, a high-power GaN/AlGaN/GaN high electron mobility transistor (HEMT) has been demonstrated. A thick cap layer has been used to screen surface states and reduce dispersion. A deep gate recess was used to achieve the desired transconductance. A thin SiO2 layer was deposited on the drain side of the gate recess in order to reduce gate leakage current and improve breakdown voltage. No surface passivation layer was used. A breakdown voltage of 90 V was achieved. A record output power density of 12 W/mm with an associated power-added efficiency (PAE) of 40.5% was measured at 10 GHz. These results demonstrate the potential of the technique as a controllable and repeatable solution to decrease dispersion and produce power from GaN-based HEMTs without surface passivation. View full abstract»

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  • Contact resistance measurement of bonded copper interconnects for three-dimensional integration technology

    Publication Year: 2004 , Page(s): 10 - 12
    Cited by:  Papers (21)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    A novel test structure for contact resistance measurement of bonded copper interconnects in three-dimensional integration technology is proposed and fabricated. This test structure requires a simple fabrication process and eliminates the possibility of measurement errors due to misalignment during bonding. Specific contact resistances of bonding interfaces with different interconnect sizes of approximately 10-8 Ω-cm2 are measured. A reduction in specific contact resistance is obtained by longer anneal time. The specific contact resistance of bonded interconnects with longer anneal time does not change with interconnect sizes. View full abstract»

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  • TDDB and polarity-dependent reliability of high-quality, ultrathin CVD HfO2 gate stack with TaN gate electrode

    Publication Year: 2004 , Page(s): 13 - 15
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB) |  | HTML iconHTML  

    In this letter, we present a comprehensive study on longterm reliability of ultrathin TaN-gated chemical vapor deposition gate stack with EOT=8.5-10.5. It is found that, due to the asymmetric band structure of HfO2 gate stack with an interfacial layer, the HfO2 gate stack shows polarity-dependent leakage current, critical defect density, and defect generation rate, under gate and substrate injection. However, no such polarity dependence of time-to-breakdown (TBD) is observed when TBD is plotted as a function of gate voltage. The 10-year lifetime of an HfO2 gate stack is projected to be Vg=-1.63 V for the equivalent oxide thickness (EOT) =8.6 and Vg=-1.88 V for EOT=10.6 at 25°C. These excellent reliability characteristics are attributed to reduced leakage current of HfO2 gate stack with physically thicker films that result in larger critical defect density and Weibull slope to that of SiO2 for the same EOT. However, at 150°C, and with area scaling to 0.1 cm2 and low percentile of 0.01%, the maximum allowed voltages are projected to Vg=-0.6 V and -0.75 V for EOT of 8.6, and 10.6, respectively. View full abstract»

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  • A new junction termination method employing shallow trenches filled with oxide

    Publication Year: 2004 , Page(s): 16 - 18
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB) |  | HTML iconHTML  

    A new junction termination method employing shallow trenches filled with oxide, which successfully decreased the junction termination area, is proposed and fabricated without any complicated process such as Si-deep etching. Shallow trenches between the floating field limiting rings successfully redistributed the single electric field peak into two peaks so that the breakdown voltage could be increased with the same junction termination area. The experimental results show that the proposed method decreased the junction termination area by more than 25% compared to a conventional field limiting ring structure when breakdown voltages are equal. View full abstract»

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  • A nondestructive approach to predict the failure time of thin-film interconnects under high-stress current

    Publication Year: 2004 , Page(s): 19 - 21
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    We describe a rapid nondestructive approach to predict the failure time for thin-film interconnects. The prediction is made on the basis of the percolation theory and the scaling model, and is verified by experimental results. Al-Cu fuses are used as our thin-film test structures that were subjected to overstressed conditions for failure. A brief description about the test structure and the experimental procedure is presented. The discrepancy between the exact failure time and the predicted failure time is significantly low, which clearly expresses the strength of this prediction technique. Moreover, this technique is nondestructive and possesses great potential to be widely used as a cost efficient and time efficient reliability test technique in semiconductor industries. View full abstract»

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  • Light guide for pixel crosstalk improvement in deep submicron CMOS image sensor

    Publication Year: 2004 , Page(s): 22 - 24
    Cited by:  Papers (6)  |  Patents (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (529 KB) |  | HTML iconHTML  

    Light guide, a novel dielectric structure consisting of PE-Oxide and FSG-Oxide, has been developed to reduce crosstalk in 0.18-μm CMOS image sensor technology. Due to the difference in refraction index (1.46 for PE-Oxide and 1.435 for FSG-Oxide), major part of the incident light can be totally reflected at the interface of PE-Oxide/FSG-Oxide, as the incidence angle is larger than total reflection angle. With this light guide, the pixel sensing capability can be enhanced and to reduce pixel crosstalk. Small pixels with pitch 3.0-μm and 4.0-μm have been characterized and examined. In 3.0-μm pixel, optical crosstalk achieves 30% reduction for incidence angle of light at 10/spl deg/. View full abstract»

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  • Poly-Si TFTs with asymmetric dual-gate for kink current reduction

    Publication Year: 2004 , Page(s): 25 - 27
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB) |  | HTML iconHTML  

    Poly-Si thin-film transistors (TFTs) with an asymmetric dual-gate, which reduces the kink current considerably, have been proposed and fabricated without any additional mask. Asymmetric dual-gate TFTs consist of a long gate and a short gate, which are located near the source and the drain, respectively. In the saturation regime, the short gate would induce the pinchoff near the drain, while the long gate may operate in the linear mode so that the kink effect only occurs at the channel under short gate. We have successfully fabricated asymmetric dual-gate TFTs and experimental results show that the kink current is successfully reduced. We also performed numerical simulation of electrical potential at the floated n+ region in order to verify the experimental result. View full abstract»

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  • A novel low-voltage N-channel heterostructure dynamic threshold voltage MOSFET (N-HDTMOS) with p-type doped SiGe body

    Publication Year: 2004 , Page(s): 28 - 30
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    A novel N-channel Si/SiGe heterostructure dynamic threshold voltage MOSFET (N-HDTMOS) has been proposed and fabricated. The Si/SiGe N-HDTMOS consists of an unstrained surface Si channel and heavily p-type doped SiGe body. The potential of the conduction band edge of the surface Si channel can be lowered by introducing a heavily p-type doped SiGe layer into a suitable position in the body region. As a result, the N-HDTMOS shows a threshold voltage reduction and a body effect factor (γ) enhancement while keeping high doping concentration in the SiGe layer. The fabricated SiGe N-HDTMOS exhibits superior properties, that is, 0.1 V reduction of Vth, 1.5 times enhancement of γ, and 1.3 times saturated current, as compared with those of Si N-DTMOS. View full abstract»

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  • Automatic control of oscillation phase of a single-electron transistor

    Publication Year: 2004 , Page(s): 31 - 33
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB) |  | HTML iconHTML  

    Automatic phase control of the Coulomb-blockade (CB) oscillation of a single-electron transistor (SET) is proposed and experimentally demonstrated. Charges in the memory node (MN) capacitively coupled to the SET control the phase of the CB oscillation. The output signal of the SET can controls chares in the MN. This feedback mechanism automatically adjusts the amount of charges, so that the output signal is leveled with a requested one for arbitrary input signal of the SET. The electrical phase control realizes the demonstration of a multifunctional Boolean logic. View full abstract»

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  • High-frequency response in carbon nanotube field-effect transistors

    Publication Year: 2004 , Page(s): 34 - 36
    Cited by:  Papers (27)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    We report electrical measurements of the radio frequency response of carbon nanotube field-effect transistors (CNFETs). The very low current drive of CNFETs makes conventional high-frequency measurements difficult. To overcome this problem, we have used a novel approach to easily measure the response up to 250 MHz in nonoptimized experimental conditions. We observe a clear response of our CNFETs with no deterioration in signal up to at least 250 MHz, which is the limit for our present configuration. View full abstract»

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  • A novel low-cost, high-efficiency micromachined silicon solar cell

    Publication Year: 2004 , Page(s): 37 - 39
    Cited by:  Papers (36)  |  Patents (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    This letter presents a new process for the fabrication of solar cells and modules from single crystal silicon wafers with substantially reduced silicon consumption and processing effort compared to conventional wafer-based cells. The technique of narrow trench etching in an alkaline solution is used to create a series of thin silicon strips extending vertically through the wafer. By turning the silicon strips on their side, a large increase in surface area is achieved. Individual cells fabricated using the new process have reached efficiencies up to 18.5% while a 575 cm2 module incorporating a rear reflector and a cell surface coverage of 50% has displayed an efficiency of 12.3% under standard rating conditions. The technique has the potential to reduce silicon consumption by a factor of 10 compared to standard wafer-based silicon solar cells and, therefore, to dramatically reduce the dependence to the expensive silicon feedstock. View full abstract»

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  • Mechanically strained strained-Si NMOSFETs

    Publication Year: 2004 , Page(s): 40 - 42
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (189 KB) |  | HTML iconHTML  

    The drain-current enhancement of the mechanically strained strained-Si NMOSFET device is investigated for the first time. The improvements of the drain current are found to be /spl sim/3.4% and /spl sim/6.5% for the strained-Si and control Si devices, respectively, with the channel length of 25 μm at the external biaxial tensile strain of 0.037%, while the drain-current enhancements are /spl sim/2.0% and /spl sim/4.5% for strained-Si and control Si devices, respectively, with the channel length of 0.6 μm. Beside the strain caused by lattice mismatch, the mechanical strain can further enhance the current drive of the strained-Si NMOSFET. The strain distribution due to the mechanical stress has different effect on the current enhancement depending on the strain magnitude and channel direction. The smaller current enhancement for strained-Si device as compared to the control device can be explained by the saturation of mobility enhancement at large strain. View full abstract»

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  • IEEE Electron Devices Society meeting calendar

    Publication Year: 2004 , Page(s): 43 - 44
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    Freely Available from IEEE
  • IEEE copyright form

    Publication Year: 2004 , Page(s): 45 - 46
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  • IEEE Electron Device Letters Information for authors

    Publication Year: 2004 , Page(s): 47
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  • Table of contents

    Publication Year: 2004 , Page(s): 48 - 49
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Aims & Scope

IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Editor-in-Chief

Amitava Chatterjee