By Topic

Solid-State Circuits, IEEE Journal of

Issue 2 • Date Feb. 2004

Filter Results

Displaying Results 1 - 24 of 24
  • Table of contents

    Publication Year: 2004 , Page(s): 0_1
    Save to Project icon | Request Permissions | PDF file iconPDF (34 KB)  
    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits publication information

    Publication Year: 2004 , Page(s): 0_2
    Save to Project icon | Request Permissions | PDF file iconPDF (36 KB)  
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2004 , Page(s): 273
    Save to Project icon | Request Permissions | PDF file iconPDF (34 KB)  
    Freely Available from IEEE
  • New Associate Editors

    Publication Year: 2004 , Page(s): 274
    Save to Project icon | Request Permissions | PDF file iconPDF (55 KB) |  | HTML iconHTML  
    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

    Publication Year: 2004 , Page(s): 275 - 282
    Cited by:  Papers (230)  |  Patents (28)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (440 KB) |  | HTML iconHTML  

    Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Calibration of phase and gain mismatches in Weaver image-reject receiver

    Publication Year: 2004 , Page(s): 283 - 289
    Cited by:  Papers (33)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    A modified image-reject Weaver architecture is presented. The design automatically calibrates for phase and gain mismatches that limit the performance of image-reject receivers. On-line or off-line calibrations are possible without using any calibrating tone. An experimental CMOS prototype RF front-end operating at 1.8 GHz achieves an image rejection ratio of 59 dB using on-line calibration. The d... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Nonlinear analysis of noise in current-steering variable gain amplifiers

    Publication Year: 2004 , Page(s): 290 - 296
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    This paper investigates the difference between the small-signal noise figure and the noise figure in the presence of a large signal at the input of a current-steering variable gain pair. The mechanism of noise generation in the presence of a large signal at the emitters of the current-steering pair is analyzed for single-ended and differential operation. An analytical equation for the large-signal... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A "divide and conquer" technique for implementing wide dynamic range continuous-time filters

    Publication Year: 2004 , Page(s): 297 - 307
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (480 KB) |  | HTML iconHTML  

    This paper presents a technique for implementing analog filters with wide dynamic range and low power dissipation and chip area. The desired dynamic range of the filter is divided into subranges, each covered by a different filtering path optimized specifically for this subrange. This results in small admittance levels for the individual filtering paths and correspondingly small power dissipation ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A micropower logarithmic A/D with offset and temperature compensation

    Publication Year: 2004 , Page(s): 308 - 319
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (888 KB) |  | HTML iconHTML  

    Logarithmic circuits are useful in many applications that require nonlinear signal compression, such as in speech recognition front-ends (SRFEs) and cochlear implants or bionic ears (BEs). A logarithmic current-input analog-to-digital converter (A/D) with temperature compensation and automatic offset calibration is presented in this paper. It employs a diode to compute the logarithm, a wide linear... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A monolithic positioning system

    Publication Year: 2004 , Page(s): 320 - 326
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (640 KB) |  | HTML iconHTML  

    A monolithic positioning system operating with absolute coded magnetic scales is presented. The system is intended for precise absolute positioning in industrial applications. Mounted on a tool, the sensor system moves along a stationary scale. A sophisticated comb of sensors reads out the magnetic coding allowing the absolute position to be calculated. The main task has been to cancel the immense... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The CMOS carry-forward adders

    Publication Year: 2004 , Page(s): 327 - 336
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (872 KB) |  | HTML iconHTML  

    The ripple-carry adder (RCA) has the simplest circuit structure but the longest delay among all adders. Thus, it is often realized with the dynamic circuits when speed is the major concern. In this paper, we propose circuit-level and architecture-level innovations over the dynamic RCA (DRCA) that lead to high operation speed and low hardware overhead. Circuit-wise, we propose a cost-effective way ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A micropower programmable DSP using approximate signal processing based on distributed arithmetic

    Publication Year: 2004 , Page(s): 337 - 347
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    A recent trend in low-power design has been the employment of reduced precision processing methods for decreasing arithmetic activity and average power dissipation. Such designs can trade off power and arithmetic precision as system requirements change. This work explores the potential of distributed arithmetic (DA) computation structures for low-power precision-on-demand computation. We present a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Computation sharing programmable FIR filter for low-power and high-performance applications

    Publication Year: 2004 , Page(s): 348 - 357
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications

    Publication Year: 2004 , Page(s): 358 - 367
    Cited by:  Papers (31)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1224 KB) |  | HTML iconHTML  

    A 121-mm2 graphics LSI is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics and MPEG-4 applications. The LSI contains a RISC processor with a multiply-accumulate unit (MAC), a 3-D rendering engine, a programmable power optimizer, and 29-Mb embedded DRAM. The chip is built in a 0.16-μm pure DRAM technology to reduce the fabrication cost. ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 24-GHz CMOS front-end

    Publication Year: 2004 , Page(s): 368 - 373
    Cited by:  Papers (136)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (336 KB)  

    This paper reports the first 24-GHz CMOS front-end in a 0.18-μm process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S11 of -21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise fi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 0.18-μm CMOS Bluetooth analog receiver with -88-dBm sensitivity

    Publication Year: 2004 , Page(s): 374 - 377
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    A CMOS Bluetooth analog low-IF receiver that includes a low-noise amplifier, image-rejection mixer, IF bandpass active filter, and programmable gain amplifier (PGA) was fabricated in a 0.18-μm bulk CMOS process. In order to achieve good sensitivity and tolerance against blocking signals, operational amplifiers were used in the active filter and PGA, the filter and PGA were interleaved to minimi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider

    Publication Year: 2004 , Page(s): 378 - 383
    Cited by:  Papers (91)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (504 KB) |  | HTML iconHTML  

    The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-μm CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme

    Publication Year: 2004 , Page(s): 384 - 387
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    This paper describes a CMOS 32-tap delay-locked delay line, realized with a shunt-capacitor circuit scheme, with an on-chip calibration circuit that allows the on-field reduction of the delay-line differential nonlinearity (DNL) down to values close to 1%. The cells are calibrated one by one in a serial way and the silicon area occupied by the calibration circuit is roughly the same as that occupi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A voltage overscaled low-power digital filter IC

    Publication Year: 2004 , Page(s): 388 - 391
    Cited by:  Papers (32)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    In this brief, we present an integrated circuit implementation of a low-power digital filter in 0.35-μm 3.3-V CMOS process. The low-power technique combines voltage overscaling (VOS) and algorithmic noise tolerance (ANT) to push the limits of energy efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput con... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Patent Abstracts

    Publication Year: 2004 , Page(s): 392 - 406
    Save to Project icon | Request Permissions | PDF file iconPDF (700 KB)  
    Freely Available from IEEE
  • IEEE Custom Integrated Circuits Conference call for papers

    Publication Year: 2004 , Page(s): 407
    Save to Project icon | Request Permissions | PDF file iconPDF (176 KB)  
    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits 30th European Solid-State Circuits Conference

    Publication Year: 2004 , Page(s): 408
    Save to Project icon | Request Permissions | PDF file iconPDF (110 KB)  
    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits information for authors

    Publication Year: 2004 , Page(s): 03
    Save to Project icon | Request Permissions | PDF file iconPDF (32 KB)  
    Freely Available from IEEE
  • [Blank page - back cover]

    Publication Year: 2004 , Page(s): 04
    Save to Project icon | Request Permissions | PDF file iconPDF (4 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan