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Solid-State Circuits, IEEE Journal of

Issue 2 • Date Feb. 2004

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Displaying Results 1 - 24 of 24
  • Table of contents

    Page(s): 0_1
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  • IEEE Journal of Solid-State Circuits publication information

    Page(s): 0_2
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  • Table of contents

    Page(s): 273
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  • New Associate Editors

    Page(s): 274
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  • Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

    Page(s): 275 - 282
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB) |  | HTML iconHTML  

    Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching device. This allows for designing wide-band impedance-matching amplifiers with NF well below 3 dB, without suffering from instability issues. An amplifier realized in 0.25-μm standard CMOS shows NF values below 2.4 dB over more than one decade of bandwidth (i.e., 150-2000 MHz) and below 2 dB over more than two octaves (i.e., 250-1100 MHz). Furthermore, the total voltage gain is 13.7 dB, the -3-dB bandwidth is from 2 MHz to 1.6 GHz, the IIP2 is +12 dBm, and the IIP3 is 0 dBm. The LNA drains 14 mA from a 2.5-V supply and the die area is 0.3×0.25 mm2. View full abstract»

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  • Calibration of phase and gain mismatches in Weaver image-reject receiver

    Page(s): 283 - 289
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    A modified image-reject Weaver architecture is presented. The design automatically calibrates for phase and gain mismatches that limit the performance of image-reject receivers. On-line or off-line calibrations are possible without using any calibrating tone. An experimental CMOS prototype RF front-end operating at 1.8 GHz achieves an image rejection ratio of 59 dB using on-line calibration. The design was fabricated in a 0.35-μm CMOS process and dissipates 160 mW from a 3-V supply during on-line calibration, and 95 mW during normal receiving. The die area is 4 mm2. View full abstract»

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  • Nonlinear analysis of noise in current-steering variable gain amplifiers

    Page(s): 290 - 296
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    This paper investigates the difference between the small-signal noise figure and the noise figure in the presence of a large signal at the input of a current-steering variable gain pair. The mechanism of noise generation in the presence of a large signal at the emitters of the current-steering pair is analyzed for single-ended and differential operation. An analytical equation for the large-signal noise figure is derived. The results are applied to a cable TV IF amplifier and compared to measured data. View full abstract»

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  • A "divide and conquer" technique for implementing wide dynamic range continuous-time filters

    Page(s): 297 - 307
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB) |  | HTML iconHTML  

    This paper presents a technique for implementing analog filters with wide dynamic range and low power dissipation and chip area. The desired dynamic range of the filter is divided into subranges, each covered by a different filtering path optimized specifically for this subrange. This results in small admittance levels for the individual filtering paths and correspondingly small power dissipation and chip area. The system provides undisturbed output during range switching, contrary to conventional automatic gain control (AGC)/filter arrangements that generate disturbances every time the gain of the AGC changes. We also report on a low-noise highly linear CMOS transconductor useful for high-frequency applications. A chip implementing the ideas of this paper was fabricated in a 0.25-μm digital CMOS process. The intended application of the filter is channel selection in an 802.11a/Hiperlan2 Wireless Ethernet receiver. The chip dissipates 9 mA, occupies an area of 0.7 mm2, and maintains a signal/(noise + IM3 distortion) ratio of at least 33 dB over a 48-dB signal range, with good blocker immunity. This performance represents at least an order of magnitude improvement over existing channel selection filters, even those that do not achieve disturbance-free operation. View full abstract»

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  • A micropower logarithmic A/D with offset and temperature compensation

    Page(s): 308 - 319
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB) |  | HTML iconHTML  

    Logarithmic circuits are useful in many applications that require nonlinear signal compression, such as in speech recognition front-ends (SRFEs) and cochlear implants or bionic ears (BEs). A logarithmic current-input analog-to-digital converter (A/D) with temperature compensation and automatic offset calibration is presented in this paper. It employs a diode to compute the logarithm, a wide linear range transconductor to perform voltage-to-current conversion, and a dual-slope auto- zeroing topology with 60 dB of dynamic range for sampling the envelope of speech signals. The temperature dependence of the logarithm inherent in a diode implementation is automatically cancelled in our circuit topology. Experimental results from a 1.5-μm 3-V BiCMOS process show that the converter achieves a temperature stability lower than 150 ppm/°C from 12°C to 42°C, and consumes only 3 μW of power when sampling at 300 Hz. At this level of power consumption, we show that the design is thermal-noise limited to 8 bits of precision. This level of precision is more than adequate for deaf patients and for speech recognition front-ends. The power consumption is almost two orders of magnitude lower than state-of-the-art DSP implementations, and the use of a local feedback topology achieves a 2.5-bit improvement over conventional dual-slope designs. View full abstract»

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  • A monolithic positioning system

    Page(s): 320 - 326
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    A monolithic positioning system operating with absolute coded magnetic scales is presented. The system is intended for precise absolute positioning in industrial applications. Mounted on a tool, the sensor system moves along a stationary scale. A sophisticated comb of sensors reads out the magnetic coding allowing the absolute position to be calculated. The main task has been to cancel the immense sensor offsets. Numerous structures have been measured in order to get statistically assured data of sensitivity and offset variation. A sensor readout technique without large offset cancellation circuitry is discussed. Furthermore a novel linear operational transconductance amplifier (OTA) is shown. View full abstract»

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  • The CMOS carry-forward adders

    Page(s): 327 - 336
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    The ripple-carry adder (RCA) has the simplest circuit structure but the longest delay among all adders. Thus, it is often realized with the dynamic circuits when speed is the major concern. In this paper, we propose circuit-level and architecture-level innovations over the dynamic RCA (DRCA) that lead to high operation speed and low hardware overhead. Circuit-wise, we propose a cost-effective way to eliminate the race problem of DRCA. Architecture-wise, we propose a new carry-forwarding scheme that combines a diagonal forwarding with the multilevel folding for dramatic speed improvement of the DRCA. Finally, a new multilevel carry-forwarding scheme is proposed to reduce the circuit complexity while keeping the speed. Based on all the proposed techniques, a 32-bit dynamic carry-forward adder (CFA32) with two-level carry forwarding is designed and fabricated with the 0.25-μm CMOS technology. The CFA32 consists of 1202 MOS transistors, and occupies only 0.017-mm2 silicon area after layout. The measurement result, which agrees with the simulation result, shows that the adder needs only 640 ps to perform an add operation under room temperature. Using the same techniques, a 64-bit carry-forward adder (CFA64) with two-level forwarding technique is also designed and simulated. The CFA64 consists of only 2502 MOS transistors, and the simulation result shows the evaluation time is only 780 ps. View full abstract»

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  • A micropower programmable DSP using approximate signal processing based on distributed arithmetic

    Page(s): 337 - 347
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    A recent trend in low-power design has been the employment of reduced precision processing methods for decreasing arithmetic activity and average power dissipation. Such designs can trade off power and arithmetic precision as system requirements change. This work explores the potential of distributed arithmetic (DA) computation structures for low-power precision-on-demand computation. We present an ultralow-power DSP which uses variable precision arithmetic, low-voltage circuits, and conditional clocks to implement a biomedical detection and classification algorithm using only 560 nW. Low energy consumption enables self-powered operation using ambient mechanical vibrations, converted to electric energy by a MEMS transducer and accompanying power electronics. The MEMS energy scavenging system is estimated to deliver 4.3 to 5.6 μW of power to the DSP load. View full abstract»

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  • Computation sharing programmable FIR filter for low-power and high-performance applications

    Page(s): 348 - 357
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm2 area. View full abstract»

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  • A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications

    Page(s): 358 - 367
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    A 121-mm2 graphics LSI is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics and MPEG-4 applications. The LSI contains a RISC processor with a multiply-accumulate unit (MAC), a 3-D rendering engine, a programmable power optimizer, and 29-Mb embedded DRAM. The chip is built in a 0.16-μm pure DRAM technology to reduce the fabrication cost. Texture-mapped 3-D graphics with perspective-correct address calculation and bilinear MIPMAP filtering can be realized while consuming the low power with the help of depth-first clock gating, address alignment logic, and embedded DRAM. Programmable clocking allows the LSI to operate in lower power modes for various applications. The chip consumes less than 210 mW, delivering 66 Mpixels/s and 264 Mtexel/s texture-mapped pixels with real-time special effects such as full-scene antialiasing and motion blur. View full abstract»

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  • A 24-GHz CMOS front-end

    Page(s): 368 - 373
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    This paper reports the first 24-GHz CMOS front-end in a 0.18-μm process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S11 of -21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise figure of 6 dB on 16 mA of dc current. The LNA's input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy. View full abstract»

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  • 0.18-μm CMOS Bluetooth analog receiver with -88-dBm sensitivity

    Page(s): 374 - 377
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    A CMOS Bluetooth analog low-IF receiver that includes a low-noise amplifier, image-rejection mixer, IF bandpass active filter, and programmable gain amplifier (PGA) was fabricated in a 0.18-μm bulk CMOS process. In order to achieve good sensitivity and tolerance against blocking signals, operational amplifiers were used in the active filter and PGA, the filter and PGA were interleaved to minimize noise, and an on-chip automatic tuner adjusts the filter frequency. Other features included a feedforward automatic gain control with rapid convergence. When connected to the digital demodulator of a BiCMOS Bluetooth transceiver, -88-dBm sensitivity was measured at 65-mW power dissipation. All blocking signal specifications were also satisfied. View full abstract»

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  • A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider

    Page(s): 378 - 383
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB) |  | HTML iconHTML  

    The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-μm CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz over the whole tuning range. View full abstract»

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  • A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme

    Page(s): 384 - 387
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    This paper describes a CMOS 32-tap delay-locked delay line, realized with a shunt-capacitor circuit scheme, with an on-chip calibration circuit that allows the on-field reduction of the delay-line differential nonlinearity (DNL) down to values close to 1%. The cells are calibrated one by one in a serial way and the silicon area occupied by the calibration circuit is roughly the same as that occupied by the delay line itself. The prototype chips, realized with a 0.6-μm CMOS technology, demonstrate the feasibility and effectiveness of the technique with a great reduction of the delay-line DNL. The nonlinearity calibration technique presented in this paper is of general use since the number and area of the shunt-capacitor configurable loads can be properly chosen according to the process mismatch parameters and the desired calibration range and resolution. View full abstract»

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  • A voltage overscaled low-power digital filter IC

    Page(s): 388 - 391
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    In this brief, we present an integrated circuit implementation of a low-power digital filter in 0.35-μm 3.3-V CMOS process. The low-power technique combines voltage overscaling (VOS) and algorithmic noise tolerance (ANT) to push the limits of energy efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40%-67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1-dB loss in SNR for a wide range of filter bandwidths (0.05fs-0.25fs, where fs is the sampling frequency). View full abstract»

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  • Patent Abstracts

    Page(s): 392 - 406
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  • IEEE Custom Integrated Circuits Conference call for papers

    Page(s): 407
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  • IEEE Journal of Solid-State Circuits 30th European Solid-State Circuits Conference

    Page(s): 408
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  • IEEE Journal of Solid-State Circuits information for authors

    Page(s): 03
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  • [Blank page - back cover]

    Page(s): 04
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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan