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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 1 • Date Jan. 2004

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2004, Page(s): 1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004, Page(s): 2
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  • Editorial

    Publication Year: 2004, Page(s):1 - 11
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  • Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

    Publication Year: 2004, Page(s):12 - 27
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (454 KB) | HTML iconHTML

    This paper describes a linear programming (LP) problem formulation applicable to the static-timing analysis of large scale synchronous circuits with level-sensitive latches. Specifically, an LP formulation for the clock period minimization problem is developed. In order to minimize the clock period of level-sensitive circuits, the simultaneous effects of time borrowing and nonzero clock skew sched... View full abstract»

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  • Timing modeling and optimization under the transmission line model

    Publication Year: 2004, Page(s):28 - 41
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (507 KB) | HTML iconHTML

    As the operating frequency increases to gigahertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a wire, it is necessary to consider the transmission line behavior for delay computation. We present in this paper, an analytical formula for the delay computation under the transmission line model. Extensive simulations with SPICE show the high fidelity of the ... View full abstract»

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  • Timing driven gate duplication

    Publication Year: 2004, Page(s):42 - 51
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (438 KB) | HTML iconHTML

    In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary inputs(PI) in topologically sorted order evaluating tuples at the input pins of... View full abstract»

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  • A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm

    Publication Year: 2004, Page(s):52 - 66
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (949 KB) | HTML iconHTML

    The use of online arithmetic was often proposed for hardware implementations of complex digital-signal processing (DSP) algorithms. However, several important issues in the design process of such algorithms using online arithmetic are rarely discussed in the literature. This paper presents these issues and provides a methodology to analyze the behavior of networks of online arithmetic modules perf... View full abstract»

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  • Substrate coupling in digital circuits in mixed-signal smart-power systems

    Publication Year: 2004, Page(s):67 - 78
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB) | HTML iconHTML

    This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such ... View full abstract»

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  • A jitter characterization system using a component-invariant Vernier delay line

    Publication Year: 2004, Page(s):79 - 95
    Cited by:  Papers (56)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB) | HTML iconHTML

    Jitter characterization has become significantly more important for systems running at multigigahertz data rates. Time and frequency domain characterization of jitter is thus a crucial element for system specification testing. Time domain jitter measurement on a data signal with subgate timing resolution can be achieved using two delay chains feeding into the clock and datalines of a series of D-l... View full abstract»

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  • Managing power consumption in networks on chips

    Publication Year: 2004, Page(s):96 - 107
    Cited by:  Papers (26)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (475 KB) | HTML iconHTML

    In this paper, we present a new methodology for managing power consumption of networks-on-chips (NOCs). A power management problem is formulated for the first time using closed-loop control concepts. We introduce an estimator and a controller that implement our power management methodology. The estimator is capable of very fast and accurate tracking of changes in the system parameters. Parameters ... View full abstract»

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  • On-chip traffic modeling and synthesis for MPEG-2 video applications

    Publication Year: 2004, Page(s):108 - 119
    Cited by:  Papers (82)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (931 KB) | HTML iconHTML

    The objective of this paper is to introduce self-similarity as a fundamental property exhibited by the bursty traffic between on-chip modules in typical MPEG-2 video applications. Statistical tests performed on relevant traces extracted from common video clips establish unequivocally the existence of self-similarity in video traffic. Using a generic tile-based communication architecture, we discus... View full abstract»

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  • A fast on-chip profiler memory using a pipelined binary tree

    Publication Year: 2004, Page(s):120 - 122
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (158 KB) | HTML iconHTML

    We introduce a novel memory architecture that can count the occurrences of patterns on a system's bus, a task known as profiling. Such profiling can serve a variety of purposes, like detecting a microprocessor's software hot spots or frequently used data values, which can be used to optimize various aspects of the system. The memory, which we call ProMem, is based on a pipelined binary search tree... View full abstract»

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  • IEEE Computer Society Annual Symposium on VLSI

    Publication Year: 2004, Page(s): 123
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  • IEEE International Symposium on Circuits and Systems (ISCAS2004)

    Publication Year: 2004, Page(s): 124
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  • The 13th International Workshop on Logic & Synthesis (IWLS)

    Publication Year: 2004, Page(s): 125
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  • International Symposium on Low Power Electronics and Design (ISLPED'04)

    Publication Year: 2004, Page(s): 126
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  • IEEE copyright form

    Publication Year: 2004, Page(s):127 - 128
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information

    Publication Year: 2004, Page(s): 3
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  • IEEE Transactions on Very Large Scale Integrated (VLSI) Systems Information for authors

    Publication Year: 2004, Page(s): 4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu