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IEEE Transactions on Computers

Issue 2 • Date Feb 2004

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Displaying Results 1 - 14 of 14
  • Delay-optimized implementation of IEEE floating-point addition

    Publication Year: 2004, Page(s):97 - 113
    Cited by:  Papers (50)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3560 KB) | HTML iconHTML

    We present an IEEE floating-point adder (FP-adder) design. The adder accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly normalized rounded sum/difference in the format required by the IEEE Standard. The FP-adder design achieves a low latency by combining various optimization techniques such as: a nonstandard separation into two paths, a simple rounding alg... View full abstract»

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  • Enhanced utilization bounds for QoS management

    Publication Year: 2004, Page(s):187 - 200
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2502 KB) | HTML iconHTML

    In many practical real-time applications, there is a given set of task frequencies (i.e., inverse of task periods) corresponding to predetermined QoS options that the applications can choose. For example, in audio applications, the typical choices of playback frequencies are for CD quality, radio quality, and phone quality. Similar configurations can be found in streaming video and in control appl... View full abstract»

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  • Power-aware branch prediction: characterization and design

    Publication Year: 2004, Page(s):168 - 186
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7587 KB) | HTML iconHTML

    This uses Wattch and the SPEC 2000 integer and floating-point benchmarks to explore the role of branch predictor organization in power/energy/performance trade offs for processor design. Even though the direction predictor by itself represents less than 1 percent of the processor's total power dissipation, prediction accuracy is nevertheless a powerful lever on processor behavior and program execu... View full abstract»

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  • DPR, LPR: proactive resource allocation algorithms for asynchronous real-time distributed systems

    Publication Year: 2004, Page(s):201 - 216
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3600 KB) | HTML iconHTML

    We present two proactive resource allocation algorithms, called DPR and LPR, for satisfying the timeliness requirements of real-time tasks in asynchronous real-time distributed systems. The algorithms are proactive in the sense that they allow application-specified and user-triggered resource allocation by allowing anticipated task workloads to be specified for future time intervals. When proactiv... View full abstract»

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  • Thread partitioning and value prediction for exploiting speculative thread-level parallelism

    Publication Year: 2004, Page(s):114 - 125
    Cited by:  Papers (9)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2143 KB) | HTML iconHTML

    Speculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find. However, the efficiency of this execution model strongly depends on the performance of the control and data speculation techniques. Several hardware-based schemes for partitioning the program into speculative threads are anal... View full abstract»

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  • The interplay of power management and fault recovery in real-time systems

    Publication Year: 2004, Page(s):217 - 231
    Cited by:  Papers (53)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3112 KB) | HTML iconHTML

    We describe how to exploit the scheduling slack in a real-time system to reduce energy consumption and achieve fault tolerance at the same time. During failure-free operation, a task takes checkpoints to enable recovery from failure. Additionally, the system exploits the slack to conserve energy by reducing the processor speed. If a task fails, it will restart from a saved checkpoint and execute a... View full abstract»

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  • A prefetch taxonomy

    Publication Year: 2004, Page(s):126 - 140
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1617 KB) | HTML iconHTML

    The growing difference between processor and main memory cycle time demands the use of aggressive prefetch algorithms to reduce the effective memory access latency. However, prefetching can significantly increase memory traffic and unsuccessful prefetches may pollute the cache. Metrics such as coverage and accuracy result from a simplistic classification of individual prefetches as "good" or "bad.... View full abstract»

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  • Efficient 1-out-of-n oblivious transfer schemes with universally usable parameters

    Publication Year: 2004, Page(s):232 - 240
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1141 KB) | HTML iconHTML

    We propose efficient and secure (string) oblivious transfer (OT1n) schemes for any n≥2. We build our OT1n scheme from fundamental cryptographic techniques directly. The receiver's choice is unconditionally secure and the secrecy of the unchosen secrets is based on the hardness of the decisional Diffie-Hellman problem. Some schemes achieve optimal effi... View full abstract»

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  • Custom wide counterflow pipelines for high-performance embedded applications

    Publication Year: 2004, Page(s):141 - 158
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4292 KB) | HTML iconHTML

    Application-specific instruction set processor (ASIP) design is a promising technique to meet the performance and cost goals of high-performance systems. ASIPs are especially valuable for embedded computing applications (e.g., digital cameras, color printers, cellular phones, etc.) where a small increase in performance and decrease in cost can have a large impact on a product's viability. Sutherla... View full abstract»

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  • A class of M-ary asymmetric symbol error correcting codes for data entry devices

    Publication Year: 2004, Page(s):159 - 167
    Cited by:  Papers (9)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (489 KB) | HTML iconHTML

    Nonbinary M-ary symbols such as alphanumeric characters are commonly used in data entry devices, e.g., keyboards and character recognition devices. The M-ary symbols processed by these devices are sometimes mistaken for other symbols due to errors such as mistyping in keyboards or misreading in character recognition systems. These errors are generally asymmetric, not symmetric. For example, the sy... View full abstract»

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 2004, Page(s): 01
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    Freely Available from IEEE
  • IEEE Transactions on Computers

    Publication Year: 2004, Page(s): 0_2
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    Freely Available from IEEE
  • Information for authors

    Publication Year: 2004, Page(s): 03
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  • IEEE Computer Society

    Publication Year: 2004, Page(s): 04
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org