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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 1 • Date Jan. 2004

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Displaying Results 1 - 25 of 35
  • Table of contents

    Publication Year: 2004 , Page(s): 01
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers Society Information

    Publication Year: 2004 , Page(s): 1
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    Freely Available from IEEE
  • The Editor's Corner

    Publication Year: 2004 , Page(s): 1 - 2
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  • Signal folding in A/D converters

    Publication Year: 2004 , Page(s): 3 - 14
    Cited by:  Papers (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    Signal folding appears in A/D converters (ADCs) in various ways. In this paper, the evolution of this technique is derived from the fundamentals of quantization to obtain systematic insights. We look upon folding as an automatic multiplexing of zero crossings, which simplifies hardware while preserving the high speed and low latency of a flash ADC. By appreciating similarities between the well-known pipeline ADCs, folding ADCs, and ripple through ADCs, this enables the circuit designer to more freely choose the best architecture to meet the specified performance goals. View full abstract»

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  • Online calibration of a Nyquist-rate analog-to-digital converter using output code-density histograms

    Publication Year: 2004 , Page(s): 15 - 24
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB) |  | HTML iconHTML  

    A scheme for the online correction of static nonlinearities in a Nyquist-rate analog-to-digital converter (ADC), using output code-density histograms, is presented. The estimation of the integral nonlinearity (INL) at each output level, followed by the creation of a corresponding entry in the look-up table for error correction, is analytically explained. The suitability of the scheme for calibrating high-end ADCs has been demonstrated. An extra ADC and the associated switching and postprocessing DSP circuitry along with some memory for storing the data to be processed, are the overhead in this scheme. An improvement of over 20 dB in the spurious-free dynamic range, from an uncalibrated value of over 80 dB, has been achieved. View full abstract»

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  • New current-mode wave-pipelined architectures for high-speed analog-to-digital converters

    Publication Year: 2004 , Page(s): 25 - 37
    Cited by:  Papers (9)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (744 KB) |  | HTML iconHTML  

    In this paper, two new architectures for high-speed CMOS wave-pipelined current-mode A/D converters (WP-IADCs) are proposed and analyzed. In the new WP-IADC architectures, the wave-pipelined theory is applied to both pipeline structures, called full WP-IADC (FWP-IADC) and indirect transfer WP-IADC (ITWP-IADC). In the FWP-IADC, each stage uses the full current-mode wave-pipelined structure without switched-current cell circuits. In the ITWP-IADC, the switched-current cells are incorporated into the wave-pipelined stages which are divided into several sections with controlled clocks. Therefore, the proposed ITWP-IADC performs optimally in terms of speed and accuracy in the WP-IADCs. Generally, the proposed WP-IADCs have the advantages of high speed, high input frequency, high efficiency of timing usage, high clock-period flexibility in switched-current cells for precision enhancement, and reduced number of switched-current cells in the overall data path for linearity improvement. According to the theoretical analysis on the proposed WP-IADC structures, the minimum sampling clock period is proportional to the intrinsic delay of the current mirror and the increased rise/fall time in each wave-pipelined stage. The HSPICE simulation results reveal that, under Nyquist rate sampling in 8-b resolution, a sampling rate of 20 and 54 MHz can be achieved for FWP-IADC and two-section ITWP-IADC, respectively. If four wave-pipelined sections are used, the ITWP-IADC can be operated at 166 MHz at an input frequency of 8 MHz. To experimentally verify the correct function of the proposed WP-IADC structures, the proposed new architecture of the FWP-IADC is implemented by using 0.35-μm CMOS technology. The measurement results successfully demonstrate the feasibility of wave-pipelined IADC architectures in applications of high-speed ADCs. View full abstract»

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  • Least mean square adaptive digital background calibration of pipelined analog-to-digital converters

    Publication Year: 2004 , Page(s): 38 - 46
    Cited by:  Papers (85)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors including capacitor mismatch, finite op-amp gain, op-amp offset, and sampling-switch-induced offset, provided they are not signal-dependent. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques. View full abstract»

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  • Highly linear 2.5-V CMOS ΣΔ modulator for ADSL+

    Publication Year: 2004 , Page(s): 47 - 62
    Cited by:  Papers (18)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB) |  | HTML iconHTML  

    We present a 90-dB spurious-free dynamic range sigma-delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-μm CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within ±0.85 and ±0.80 LSB14 b, respectively. The ΣΔ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the ΣΔ modulator. View full abstract»

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  • An efficient ΔΣ ADC architecture for low oversampling ratios

    Publication Year: 2004 , Page(s): 63 - 71
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB) |  | HTML iconHTML  

    As the demand for ΔΣ (delta-sigma) analog-to-digital converters (ADCs) with higher bandwidth and higher signal-to-noise ratio (SNR) increases, designers have to look for efficient structures with low oversampling ratio (OSR). The Leslie-Singh or M-0 MASH architecture is often used in such applications. Based on this architecture, a reduced-sample-rate structure was introduced, which needs less chip area and power, but increases the noise floor. This paper describes a modification of the reduced-sample-rate structure which realizes an optimized transfer function, and avoids an SNR loss. In fact, it increases the SNR for high-order modulators. The method can also be applied to one-stage modulators. Simulation results for different MASH ADCs and sensitivity analysis verify the usefulness of the proposed technique. View full abstract»

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  • High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications

    Publication Year: 2004 , Page(s): 72 - 85
    Cited by:  Papers (66)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    High-speed high-resolution ΔΣ analog-to-digital converters (ADCs) for broad-band communication applications must be designed at a low oversampling ratio (OSR). However, lowering the OSR limits the efficiency of a ΔΣ ADC in achieving a high-resolution A/D conversion. This paper presents several techniques that enable the OSR reduction in ΔΣ ADCs without compromising the resolution. 1) Noise transfer function (NTF). In this paper, a single-stage multibit ΔΣ modulator with a high-order finite-impulse-response NTF is proposed to achieve high signal-to-quantization-noise ratios at low OSRs. Its key features include: decreased circuit complexity, improved robustness to modulator coefficient variations, and reduced sensitivity to integrator nonlinearities. Its performance is validated through behavioral simulations and compared to traditional ΔΣ modulator structures. 2) Signal transfer function (STF). This paper describes how the STF of a ΔΣ modulator can be designed, independently of the NTF, in order to significantly reduce the harmonic distortion due to opamp nonidealities and to help lower the power dissipation. 3) Dynamic element matching (DEM) is also presented. Data weighted averaging (DWA) has prevailed as the most practical DEM technique to linearize the internal digital-to-analog converter (DAC) of a multibit ΔΣ modulator, especially when the number of DAC elements is large. However, the occurrence of in-band signal-dependent tones, when using DWA at a low OSR, degrades the spurious-free dynamic range. This paper proposes a simple technique, called pseudo DWA, to solve the DWA tone problem without sacrificing the signal-to-noise ratio. Its implementation adds no extra delay in the ΔΣ feedback loop and requires only minimal additional digital hardware. Existing schemes for DWA tone reduction are also compared. View full abstract»

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  • Systematic design exploration of delta-sigma ADCs

    Publication Year: 2004 , Page(s): 86 - 95
    Cited by:  Papers (23)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    An algorithm for architecture-level exploration of the ΔΣ A/D converter (ADC) design space is presented. Starting from the desired specification, the algorithm finds an optimal solution by exhaustively exploring both single-loop and cascaded architectures, with a single-bit or multibit quantizer, for a range of oversampling ratios. A fast filter-level step evaluates the performance of all loop-filter topologies and passes the accepted solutions to the architecture-level optimization step which maps the filters on feasible architectures and evaluates their performance. The power consumption of each accepted architecture is estimated and the best top-ten solutions in terms of the ratio of peak signal-to-noise+distortion ratio versus power consumption are further optimized for yield. Experimental results for two different design targets are presented. They show that previously published solutions are among the best architectures for a given target but that better solutions can be designed as well. View full abstract»

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  • Design of low-voltage MOSFET-only ΣΔ modulators in standard digital CMOS technology

    Publication Year: 2004 , Page(s): 96 - 109
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1064 KB) |  | HTML iconHTML  

    A design strategy of low-voltage high-linearity MOSFET-only ΣΔ modulators in standard digital CMOS technology is presented. The modulators use substrate-biased MOSFETs in the depletion region as capacitors, linearized by different compensation techniques. This work shows the design, simulation and measured results of a number of MOSFET-only ΣΔ modulators using different implementations of so called compensated depletion-mode MOS capacitors. The modulators are designed for the demands of speech band applications. The performance of the modulators proves the capability of compensated depletion-mode MOS capacitors to fulfill analog circuit requirements at low supply voltages with reduced processing efforts. View full abstract»

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  • A realization of a below-1-V operational and 30-MS/s sample-and-hold IC with a 56-dB signal-to-noise ratio by applying the current-based circuit approach

    Publication Year: 2004 , Page(s): 110 - 117
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB) |  | HTML iconHTML  

    This paper demonstrates the low-voltage and low-power operation of a MOS sample-and-hold circuit while preserving speed and accuracy, aiming at the realization of a pipelined low-voltage and low-power analog-to-digital converter on a system large-scale integrated circuit. It was fabricated by utilizing 0.35-μm CMOS technology. The main feature of this circuit is that all the input, signals, and output are in the current form. The circuit consists of simple current mirrors. In order to eliminate the signal-dependent current transfer ratio error, voltages at the drain terminals of mirror transistors are fixed as constant. A source degeneration resistor, which is a transistor in the triode operational region, is connected to a mirror transistor in order to alleviate the influence of the threshold and transconductance parameter variations. Control signals are boosted in voltage and applied to the gate of switch NMOS transistors in the signal path in order to reduce the on-resistance of analog switches. A differential configuration is adopted throughout the entire circuit and effectively cancels switch feedthrough errors. As a result, a 30-MS/s operation with a signal-to-noise ratio (SNR) of 56 dB from a 1-V supply has been achieved, when the input current is ±200 μA. The chip even operated down to 0.85 V with a 20-MHz clock. The SNR was measured as 50 dB with an input current of ±100 μA. View full abstract»

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  • Sampling and signal reconstruction circuits performing internal antialiasing filtering and their influence on the design of digital receivers and transmitters

    Publication Year: 2004 , Page(s): 118 - 129
    Cited by:  Papers (28)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    Sampling and signal reconstruction circuits performing internal antialiasing filtering are derived and analyzed within the same paradigm. Their capabilities are evaluated. The practical realization of these circuits and their influence on the design of digital receivers and transmitters are considered. View full abstract»

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  • Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter

    Publication Year: 2004 , Page(s): 130 - 139
    Cited by:  Papers (73)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    Offset mismatch, gain mismatch, and sample-time error between time-interleaved channels limit the performance of time-interleaved analog-to-digital converters (ADCs). This paper focuses on the sample-time error. Techniques for correcting and detecting sample-time error in a two-channel ADC are described, and simulation results are presented. View full abstract»

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  • Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs

    Publication Year: 2004 , Page(s): 140 - 150
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB) |  | HTML iconHTML  

    Using several analog-to-digital converters (ADCs) in parallel with convenient time offsets is considered an efficient way to push the speed limits of data acquisition systems. However, a serious drawback of this time-interleaving technique is that any mismatch between the channels will damage the precision. This paper gives a probabilistic description of the problem, studying the impact of time skews, gain, and offset mismatches. The probability density function of both signal-to-noise ratio (SNR) and spurious-free-dynamic range (SFDR) are explicitly calculated, giving access to important statistical parameters. It is shown that the SNR and SFDR dispersion should not be neglected in making practical considerations for design decisions. View full abstract»

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  • Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system

    Publication Year: 2004 , Page(s): 151 - 158
    Cited by:  Papers (59)  |  Patents (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    To significantly increase the sampling rate of an A/D converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the mismatch errors. The estimation method requires no knowledge about the input signal except that it should be bandlimited to the Nyquist frequency for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the mismatch errors. The estimation method has been validated with simulations and measurements from a time-interleaved ADC system. View full abstract»

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  • Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure

    Publication Year: 2004 , Page(s): 159 - 169
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    This paper presents an improved modeling of the effect of random mismatch and current source transient switching behavior on the performance of current-steering CMOS digital-to-analog converters (DACs). The work considers two current source cell topologies, namely a simple cell and a cascoded cell, obtaining the relation of transistors design parameters to the static and dynamic models. On the one hand, a mismatching statistical analysis is applied to all the transistors of the current source circuit, which allows to define design expressions relating the circuit parameters to the DAC specifications without the need of arbitrary design margins or Monte Carlo simulations. On the other hand, improved analysis of the current source switching characteristics provides a more realistic modeling of the relation between transistors sizes and output current settling time. By including these two improved models into the usual design procedure, circuit sizing for optimum settling time and proper static behavior can be obtained analytically, reverting in smaller current source area, and, hence, in an overall DAC area reduction. View full abstract»

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  • Self-tuning algorithms for high-performance bandpass switched-capacitor ΣΔ modulators

    Publication Year: 2004 , Page(s): 170 - 174
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    Switched-capacitor high-frequency bandpass ΣΔ modulators could suffer from capacitor mismatch, finite opamp dc gain, and finite opamp bandwidth. These problems make the notch frequency and the quality factor of the zeros of the noise transfer function to deviate from their nominal values, strongly affecting the modulator dynamic range (DR). In order to avoid this situation, two sampled-data algorithms have been developed which allow to self-calibrate the bandpass ΣΔ modulators. They use 3500 gate and 0.043 mm2 area and consume power only when they are active, while, when the system is on, they are off and do not interfere with standard operation. The validity of the proposal is demonstrated by a silicon prototype in which the proposed solution allows to guarantee a 75-dB DR performance also under worst case conditions. In the particular case, it allows for the recovery of 3 dB in the SNR for the 200-kHz FM band (from 73 to 76 dB). View full abstract»

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  • An ultralow-power switched opamp-based 10-B integrated ADC for implantable biomedical applications

    Publication Year: 2004 , Page(s): 174 - 177
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    This paper describes an ultralow-power switched opamp-based integrated analog-to-digital converter (ADC) for cardiac pacemakers applications. The ADC consumption, measured on 10 chip samples and averaged, is 8.18 μW (stand-by value: 1 nW) for the analog part and of 9.71 μW (5 nW) for the digital one, using a supply battery of 2.8 V. The converter has a resolution of 10-b, its typical operating clock frequency is 32 KHz (2.9 KS/s sampling rate) and is able to reach the same resolution at 2 V (0.7 KS/s sampling rate), with a dissipation of 1 μW and 1.3 μW for analog and digital part, respectively. View full abstract»

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  • Linear phase reconstruction filtering using a hold time longer than one sample period

    Publication Year: 2004 , Page(s): 178 - 181
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    In digital-to-analog converters (DACs), the sinc frequency response of the zeroth-order sample-and-hold causes a linear-phase notch response at f=1/Th, where Th is the hold time. In this brief, this notch is used to attenuate the lowest image signal below the sampling frequency by increasing the hold time longer than one sample period. This is implemented by using two time-interleaved DACs and a gated summing circuit with programmable on-times. The level of the spurious signals caused by mismatches between the parallel branches are analyzed, and the operation of the principle is verified experimentally. View full abstract»

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  • Dynamic MOS sigmoid array folding analog-to-digital conversion

    Publication Year: 2004 , Page(s): 182 - 186
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    A dynamic, saturating difference circuit for large-scale parallel folding analog-to-digital conversion is presented. The circuit comprises a subthreshold nMOS transistor source-coupled to a capacitor, implementing a log-domain integrator. The output current is a logistic sigmoidal function of the change in voltage on the gate. Offset and gain of the differential sigmoid are controlled by timing of global clock signals and are independent of transistor mismatch. Folding operation for analog-to-digital conversion is obtained by differentially combining and integrating currents from a bank of sigmoid units. A 128-channel parallel bank of 4-bit Gray-code folding analog-to-digital converters measures 0.75 mm×2 mm in 0.5 μm CMOS and delivers 768 Msps at 82-mW power dissipation. View full abstract»

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  • A layout structure for matching many integrated resistors

    Publication Year: 2004 , Page(s): 186 - 190
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    A proposed mirrored shuffle layout pattern cancels systematic resistor gradient variations up to second order and allows monolithic integration of hundreds of matched resistors for precision analog circuits. A test circuit uses 15 000 subresistors and three levels of interconnect to form 150 main resistors in a 2.85×0.83 mm2 area. It demonstrates better than 11-b matching. The dominant remaining error is related to a layout artifact external to the core resistor array, and after separation the resistor array itself achieves over 13-b matching. Wafer maps show significant first- and second-order resistor value gradients that are cancelled to within the measurement error. View full abstract»

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  • A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC

    Publication Year: 2004 , Page(s): 191 - 195
    Cited by:  Papers (15)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    This brief analyzes the systematic errors that limit the intrinsic accuracy of a digital-to-analog converter (DAC). A new switching scheme is proposed that exhibits special properties: it cancels the linear and quadratic gradient errors at the MSB level. We explain why this scheme has those properties and how to construct it. This scheme excels at reducing edge-effects occurring at the side of the array. No extracted information from the error profile is required. This increases the robustness of the scheme and reduces the need for reprocessing. The effectiveness of this scheme is demonstrated by applying it to the measured error profile of a 14-b current-steering converter without dummies. This shows that 14-b current-steering converters can be constructed without any dummy rows or columns at all. View full abstract»

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  • A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell

    Publication Year: 2004 , Page(s): 196 - 200
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    This brief discusses the economical design of a 14-b current-steering digital-to-analog converter (DAC) macrocell for integration with other analog and digital macrocells in a system-on-chip (SOC). The DAC design is targeted for a standard 0.13-μm six-metal single-poly CMOS process. A novel algorithm sets the switching order of individual current sources and minimizes systematic mismatch errors. The design approach minimizes total fabrication cost of the SOC without a loss to specified DAC design requirements. Total macrocell design area is 2.9 mm2. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras