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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 8 • Aug. 1991

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Displaying Results 1 - 13 of 13
  • Channel density reduction by routing over the cells

    Publication Year: 1991, Page(s):1067 - 1071
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    An approach for reducing the density of a channel by routing some nets (or subnets) over the cells (i.e., outside the channel) is proposed. It is shown that only the removal of critical nets contributes to the reduction in the channel density. The channel is divided into zones, each having a zone density where the removal of any net from a zone will reduce its density by one. To reduce the channel... View full abstract»

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  • Comments on "Asymptotic waveform evaluation for timing analysis

    Publication Year: 1991, Page(s):1078 - 1079
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (177 KB)

    For the original article see ibid., vol.9, no.4, p.352-66 (1990). The commenter notes that in the above-titled paper L. Pillage and R. Rohrer employ the moment-matching technique to provide different models of different accuracies for a given linear network, the general form of which is often referred to as the Pade approximation. He briefly points out the shortcomings of the Pade approximation an... View full abstract»

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  • Optimality of a feedthrough assignment algorithm in a CMOS logic cell layout

    Publication Year: 1991, Page(s):982 - 993
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (900 KB)

    Three kinds of feedthrough assignment algorithm are suggested for CMOS logic cell layout, and their solutions and processing times are compared. One is based on the idea that the feedthrough requirement with fewest feedthrough candidates is first assigned. The second is an optimum algorithm that solves the problem by formalizing it as an integer programming problem. The third is a combination of t... View full abstract»

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  • Design of robustly testable combinational logic circuits

    Publication Year: 1991, Page(s):1036 - 1048
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1208 KB)

    An integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests is proposed. Robustly testable static CMOS primitive logic circuit designs are presented for any arbitrary combinational logic function. They require no special gates, and fan-in and fan-out constraints do not af... View full abstract»

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  • On the k-layer planar subset and topological via minimization problems

    Publication Year: 1991, Page(s):972 - 981
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (924 KB)

    Two closely related problems important for performance-driven layout design, the k-layer planar subset problem (k-PSP) and the k-layer topological via minimization problem, are studied. It is shown that both are NP-complete. Moreover, both problems can be solved in polynomial time when the routing regions are crossing channels. It can be shown that under a suita... View full abstract»

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  • Circuit width, register allocation, and ordered binary decision diagrams

    Publication Year: 1991, Page(s):1059 - 1066
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    The relationship between two important means of representing Boolean functions, combinational circuits and ordered binary decision diagrams (OBDDs), is studied. Circuit width is related to OBDD size. and it is shown how algorithms for register allocation can be used to determine a good variable order for OBDD construction. In particular, it is shown that if C has n inputs, m<... View full abstract»

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  • Buried-channel MOSFET model for SPICE

    Publication Year: 1991, Page(s):1015 - 1035
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1304 KB)

    A buried-channel (BC) MOSFET model for DC, transient and small-signal circuit simulation, which has been incorporated into SPICE 3B1, is presented. The model includes all of the modes of operation inherent to the BC-MOSFET, including the partial modes of operation. The equivalent circuit for the BC-MOSFET is presented, and the static, transient, and small-signal equations used for SPICE implementa... View full abstract»

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  • The fault dropping problem in concurrent event-driven simulation

    Publication Year: 1991, Page(s):968 - 971
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The dynamic removal of faults before the end of the test pattern is reached, called fault dropping (FD), is considered. The conventional technique, called synchronous FD, is analyzed. An asynchronous FD method is introduced and its performance compared with that of the conventional method. It is based on the concept of removing descriptors while the simulation procedures access the data structure.... View full abstract»

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  • LiB: a CMOS cell compiler

    Publication Year: 1991, Page(s):994 - 1005
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1076 KB)

    An automatic layout generation system, called LiB, for the small-scale integrated (SSI) cells used in CMOS VLSI design, is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a mask layout in CIF. The layout style is a modification of that proposed by T. Uehara, and W. M. van Cleemput (IEEE Trans. Comput., vol.C-30, no.5, p.305-12, 1981). An optimal transistor cha... View full abstract»

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  • Near optimal factorization of Boolean functions

    Publication Year: 1991, Page(s):1072 - 1078
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    An algorithm for algebraic factorization of single-output functions is presented. The algorithm is based on the generation of some products covering a set of true cubes suitably chosen. The products forming a near-optimal factored expression are locally chosen from the ones covering each of those cubes. In order to obtain a good factorization, heuristics are used in the three procedures of which t... View full abstract»

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  • An efficient algorithm for parametric fault simulation of monolithic IC's

    Publication Year: 1991, Page(s):1049 - 1058
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    An efficient methodology for performing fault simulation experiments as part of an IC failure diagnosis system is described. The methodology uses regression models that relate IC performance directly to process disturbances inherent in all IC fabrication processes. An efficient algorithm for establishing the structure of such models based on data obtained from coupled process and circuit simulator... View full abstract»

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  • The ellipsoidal technique for design centering and region approximation

    Publication Year: 1991, Page(s):1006 - 1014
    Cited by:  Papers (54)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    A technique for design centering and feasible region approximation that is based on generating a sequence of ellipsoids of decreasing volume and preserves the property of containing a bounded convex feasible region is introduced. The technique converges to an ellipsoid the center of which is the proposed design center. The ellipsoid matrix can be used to give what is called a preferable covariance... View full abstract»

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  • Consistency checking and optimization of macromodels

    Publication Year: 1991, Page(s):957 - 967
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB)

    A systematic methodology for automatic consistency checking and optimization of parameterized macromodels is described. An overview of the entire macromodel verification system. iMAVERICK, is provided. An efficient stochastic algorithm to optimize the parameters of a given macromodel is described, and a number of characteristics of the algorithm are examined. A heuristic measure of the likelihood ... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu