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Computers and Digital Techniques, IEE Proceedings -

Issue 4 • Date 18 July 2003

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Displaying Results 1 - 7 of 7
  • Handshake protocol using return-to-zero data encoding for high performance asynchronous bus

    Publication Year: 2003 , Page(s): 245 - 251
    Cited by:  Papers (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (488 KB)  

    In SoC design, synchronous buses are used frequently to interconnect several IPs. However, it is difficult to use synchronous buses for SoC design because of the increase of wire delay caused by the crosstalk effect and the difficulty of synchronisation caused by the clock-skew problem. The use of an asynchronous bus is an alternative solution for SoC design methodology. A new handshake protocol i... View full abstract»

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  • Dual multiple-polynomial LFSR for low-power mixed-mode BIST

    Publication Year: 2003 , Page(s): 209 - 217
    Cited by:  Papers (10)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (663 KB)  

    Mixed-mode BIST offers complete fault coverage with short test application times and small test data requirements. Reducing power dissipation during testing is becoming necessary for decreasing the risks of reliability problems and manufacturing yield loss. Several techniques have been recently proposed for reducing power dissipation during BIST. The work presented addresses the problem of reducin... View full abstract»

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  • Interactive built-in self-test compression for testing a system-on-a-chip

    Publication Year: 2003 , Page(s): 189 - 200
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (805 KB)  

    A methodology for test data compression and decompression in an interactive built-in self-test (iBIST) environment is presented. This methodology not only takes advantage of the strength of BIST in compression and test execution, but also overcomes BIST weaknesses by making it externally controllable. The data compression technique is realised in two steps. The first step consists of developing da... View full abstract»

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  • Multilevel logic simplification based on a containment recursive paradigm

    Publication Year: 2003 , Page(s): 218 - 226
    Cited by:  Papers (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (667 KB)  

    Multilevel logic simplification plays a very important role to achieve high quality digital circuits in the design flow of application specific integrated circuit or a field programmable gate array products. The fundamental concept of unateness, is extended to the concept of containment for Boolean functions. Accordingly, the unate recursive paradigm, which is successfully employed in the two-leve... View full abstract»

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  • Generic architecture and semiconductor intellectual property cores for advanced encryption standard cryptography

    Publication Year: 2003 , Page(s): 239 - 244
    Cited by:  Papers (5)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (490 KB)  

    A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) ele... View full abstract»

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  • Scalable techniques for system-level cosimulation and coestimation

    Publication Year: 2003 , Page(s): 227 - 238
    Cited by:  Papers (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (891 KB)  

    A system-level design approach that enforces a separation between system behaviour and architecture is presented. The system designer focuses first on system behaviour, then looks for a suitable architecture to implement it, and finally verifies the performance. Techniques and tools are described to accurately evaluate the performance of a system at different levels of abstraction. The evaluation ... View full abstract»

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  • Built-in self-repair techniques for embedded RAMs

    Publication Year: 2003 , Page(s): 201 - 208
    Cited by:  Papers (4)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (547 KB)  

    An efficient built-in self-repair approach, column-block-level reconfiguration methodology, is proposed. It is based on the concept of divided bit-line (DBL) for high-capacity memories including SRAMs and DRAMs, widely used in low-power memory designs. However, the inherent characteristics (two or more memory cells are combined together to divide the bit-line into several sub bit-lines) of divided... View full abstract»

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