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IEE Proceedings - Computers and Digital Techniques

Issue 6 • Date 17 Nov. 2003

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Displaying Results 1 - 6 of 6
  • Area and performance analysis of value predictors

    Publication Year: 2003, Page(s):375 - 386
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (326 KB)

    Value predictors that predict the results of instructions before their execution, have been proposed to improve the instruction-level parallelism at the microarchitecture level. Value predictors are categorised into static and dynamic predictors according to the type of classification of the instructions. At the expense of performance improvement, however, value predictors require extra area cost.... View full abstract»

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  • Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion

    Publication Year: 2003, Page(s):397 - 402
    Cited by:  Papers (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (252 KB)

    Based on the features of coincidence operation, a canonical OR coincidence (COC) expansion of logical functions in the OR-coincidence algebraic system is proposed, and its mapping expression (dj-map) is given. Then two new operations are introduced and the matrix form of COC expansion is discussed. This paper also introduces the mapping transform between COC expansion and maxterm expans... View full abstract»

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  • Arithmetic binary to residue encoders for moduli (2n±2k+1)

    Publication Year: 2003, Page(s):369 - 374
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (264 KB)

    A binary-to-residue encoder design that encodes the binary value into modulo (2n±2k+1) residue digits is introduced. Such encoders are important for the newly introduced moduli set: (2n,2n-1,2n+1,2n-2k+1,2n+2k+1), where k is a positive integer, and n=2k-1. The proposed design utilises n bit ca... View full abstract»

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  • Run-length coding extensions for high performance hardware data compression

    Publication Year: 2003, Page(s):387 - 395
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (394 KB)

    The optimal placement of a run-length coding extension to a dictionary-based lossless data compression algorithm is investigated. A hardware implementation of the proposed extension is completed and integrated into an existing design. The new hardware is benchmarked against commercially available software and hardware compression methods. Run-length coding replaces repetitive, identical sequences ... View full abstract»

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  • Efficient digital implementation of the sigmoid function for reprogrammable logic

    Publication Year: 2003, Page(s):403 - 411
    Cited by:  Papers (30)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (373 KB)

    Special attention must be paid to an efficient approximation of the sigmoid function in implementing FPGA-based reprogrammable hardware-based artificial neural networks. Four previously published piecewise linear and one piecewise second-order approximation of the sigmoid function are compared with SIG-sigmoid, a purely combinational approximation. The approximations are compared in terms of speed... View full abstract»

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  • Architectures for Montgomery's multiplication

    Publication Year: 2003, Page(s):361 - 368
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (333 KB)

    Many public key cryptographic algorithms require modular multiplication of very large operands as their core arithmetic operation. One method to perform this operation reasonably fast is to use specialised hardware. However, larger sizes are often required to increase security. This comes at the expense of either reducing the clock rate or dramatically increasing the size and hence the cost of the... View full abstract»

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