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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 11 • Date Nov. 2003

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Title History

Guest editorial

Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation

A behavioral modeling approach to the design of a low jitter clock source

Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach

A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop

Analytical model and behavioral simulation approach for a ΣΔ fractional-N synthesizer employing a sample-hold element

Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process

Methodology for on-chip adaptive jitter minimization in phase-locked loops

Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery

A false-lock-free clock/data recovery PLL for NRZ data using adaptive phase frequency detector

Analysis of PLL clock jitter in high-speed serial links

Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs

A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise

Techniques for in-band phase noise reduction in ΔΣ synthesizers

On the analysis of ΔΣ fractional-N frequency synthesizers for high-spectral purity

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