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IEEE Design & Test of Computers

Issue 6 • Date Nov.-Dec. 2003

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Displaying Results 1 - 14 of 14
  • Guest editors' introduction: clockless VLSI systems

    Publication Year: 2003, Page(s):5 - 8
    Cited by:  Papers (1)
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    Freely Available from IEEE
  • Three generations of asynchronous microprocessors

    Publication Year: 2003, Page(s):9 - 17
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    We trace the evolution of Caltech asynchronous processors from a simple proof of concept, to a high-performance MIPS-like processor using a different buffer circuit for better performance, to the latest 8051 clone targeting low-energy operation. We describe the control aspects of the evolving circuit styles. We describe these three generations of asynchronous microprocessors (Caltech asynchronous ... View full abstract»

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  • Reducing power dissipation, delay, and area in logic circuits by narrowing transistors

    Publication Year: 2003, Page(s):18 - 25
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (249 KB) | HTML iconHTML

    An important aspect of fast CMOS logic-circuit design is transistor sizing. Designers routinely set transistor channel lengths at the minimal values the process permits (unless there is a need to introduce delay). Specification of channel widths, however, requires careful consideration and is based mainly on the capacitive load the circuit must drive and on considerations of energy dissipation and... View full abstract»

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  • Design and characterization of null convention self-timed multipliers

    Publication Year: 2003, Page(s):26 - 36
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (302 KB) | HTML iconHTML

    We present various 4-bit /spl times/ 4-bit unsigned multipliers designed using the delay-insensitive null convention logic (NCL) paradigm. They represent bit-serial, iterative, and fully parallel multiplication architectures. NCL is a self-timed logic paradigm in which control is inherent in each datum. NCL follows the so-called weak conditions of Seitz's delay-insensitive signaling scheme. Like o... View full abstract»

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  • Cycle decomposition in NCL

    Publication Year: 2003, Page(s):38 - 43
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB) | HTML iconHTML

    In null convention logic (NCL) circuits, cycles are the fundamental unit of data storage, roughly equivalent to combinational logic bounded by latches in clocked design. Implementing the various tools common to IC design flows, such as static timing analysis and scan insertion, requires accurately identifying these cycles. Threshold gates are the basic building blocks of NCL cycles. To date, mecha... View full abstract»

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  • Implementation of a self-timed segmented bus

    Publication Year: 2003, Page(s):44 - 50
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    We propose an asynchronous structure for implementation on a SoC. An intersegment topological arrangement preserves parallelization and, through a so-called central arbiter, efficiently organizes communication with high signaling speed in the proposed structure. Researchers proposed the concept of segmenting buses primarily for multicomputer architectures. More recent approaches address on-chip im... View full abstract»

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  • Automating wave-pipelined circuit design

    Publication Year: 2003, Page(s):51 - 58
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (287 KB) | HTML iconHTML

    Wave pipelining offers faster clock rates than conventional pipelining; however, wave-pipelined circuit design is time-consuming and requires a high level of expertise. Wave pipelining is especially vulnerable to delay changes due to variations in process, voltage, and temperature (PVT) and in the operating environment. Wave pipelining's performance is also affected by the minimum-delay path. Thus... View full abstract»

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  • The tides of EDA

    Publication Year: 2003, Page(s):59 - 75
    Cited by:  Papers (15)
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    Freely Available from IEEE
  • Fabless or IDM? what the future holds for both

    Publication Year: 2003, Page(s):76 - 85
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  • What is the next implementation fabric?

    Publication Year: 2003, Page(s):86 - 95
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB) | HTML iconHTML

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  • How much variability can designers tolerate?

    Publication Year: 2003, Page(s):96 - 97
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (226 KB) | HTML iconHTML

    Designers hate large variations in a gate's critical dimensions (CDs) because large variations imply large guardbanding in design. Lithographers hate small variations in CD numbers because they imply impossible process windows. With the publication of the 2003 International Technology Roadmap for Semiconductors (1TRS), gate CD control requirements for lithography and front-end (etching) processes ... View full abstract»

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  • New advanced library format standard approved

    Publication Year: 2003, Page(s):98 - 99
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    Freely Available from IEEE
  • Author index

    Publication Year: 2003, Page(s):108 - 111
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  • Subject index

    Publication Year: 2003, Page(s):111 - 119
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty