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Computers and Digital Techniques, IEE Proceedings -

Issue 5 • Date 22 Sept. 2003

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Displaying Results 1 - 13 of 13
  • Low-cost software-based self-testing of RISC processor cores

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (238 KB)  

    Software self-testing of embedded processor cores, which effectively partitions the testing effort between low-speed external equipment and internal processor resources, has been recently proposed as an alternative to classical hardware built-in self-test techniques over which it provides significant advantages. A low-cost software-based self-testing methodology for processor cores is presented with the aim of producing compact test code sequences developed with a limited engineering effort and achieving a high fault coverage for the processor core. The objective of small test code sequences is directly related to the utilisation of low-speed external testers, since test time is primarily determined by the time required to download the test code to the processor memory at the tester's low frequency. Successful application of the methodology to an RISC processor core architecture with a three-stage pipeline is demonstrated View full abstract»

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  • Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip

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    Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional interconnects, such as networks on chip (NoC), must be used. It is shown that guaranteed services are essential in achieving this decoupling. Guarantees typically come at the cost of lower resource utilisation. To avoid this, they must be used in combination with best-effort services. The key element of this NoC is a router consisting conceptually of two parts; the so-called guaranteed-throughput (GT) and best-effort (BE) routers. The GT and BE router architectures are combined in an efficient implementation by sharing resources. The trade-offs between hardware complexity and efficiency of the combined router are shown that motivate the choices. The reasoning for the trade-offs is validated with a prototype router implementation. A layout is shown of an input-queued wormhole 5×5 router with an aggregate bandwidth of 80 Gbit/s. It occupies 0.26 mm2 in a 0.13 μm technology. This shows that our router provides high performance at reasonable cost, bringing NoCs one step closer View full abstract»

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  • Schedulability analysis and optimisation for the synthesis of multi-cluster distributed embedded systems

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    An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches View full abstract»

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  • Masking the energy behaviour of encryption algorithms

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    Smart cards are vulnerable to both noninvasive attacks using power and timing measurements to extract the cryptographic key. The power measurement techniques rely on the data-dependent energy behaviour of the underlying system. Further, power analysis can be used to identify the specific portions of the program being executed to induce timing glitches that may in turn help to bypass key checking. Thus, it is important to mask the energy consumption when executing the encryption algorithms. The instruction set architecture of a simple five-stage pipelined smart card processor with secure instructions to mask the energy differences due to key-related data-dependent computations in DES and Rijndael encryptions is augmented. The secure versions operate on the normal and complementary versions of the operands simultaneously to mask the energy variations due to value-dependent operations. However, this incurs the penalty of increased overall energy consumption in the data-path components. Consequently, we employ secure versions of instructions only for critical operations; that is we use secure instructions selectively, as directed by an optimising compiler. Using a cycle-accurate energy simulator, the effectiveness of this enhancement is demonstrated. The approach achieves energy masking of critical operations, consuming 83% less energy compared to existing approaches employing dual rail circuits View full abstract»

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  • Behavioural specifications allocation to minimise bit level waste of functional units

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    Conventional synthesis algorithms produce schedules balanced in the number of operations executed per cycle and allocate operations to functional units of their same type and width. In most implementations some hardware waste appears, because some functional units are not used in all clock cycles. This waste is even greater when multiple precision specifications, i.e. those formed by operations of different widths, are synthesised, because some bits of the results produced must be discarded in some cycles. The allocation algorithm proposed minimises this waste by increasing the reuse of hardware resources. It extracts, prior to the allocation, the common operative kernel of specification operations, and successively breaks down operations into sets of smaller ones such that functional units reuse is possible in other parts of the schedule. These transformations produce new operations whose types and widths may be different from the original ones. In consequence, some specification operations are finally executed over a set of functional units linked by some glue logic. Experimental results show that the implementations proposed by our algorithm need a considerably smaller area than those proposed by conventional allocation algorithms. Also, due to operation transformations, the type, number, and width of the hardware resources in the datapaths produced may be different from the type, number, and width of the specification operations and variables. Additionally, an analytical method to estimate the area potentially saved by our algorithm in comparison to conventional ones is developed View full abstract»

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  • Development and application of design transformations in ForSyDe

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    The formal system design (ForSyDe) methodology has been developed for system level design. Starting with a formal specification model, which captures the functionality of the system at a high level of abstraction, it provides formal design transformation methods for a transparent refinement process of the specification model into an implementation model which is optimised for synthesis. The formal treatment of transformational design refinement is the central contribution of this article. Using the formal semantics of ForSyDe processes we introduce the term characteristic function to be able to define and classify transformations as either semantic preserving or design decision. We also illustrate how we can incorporate classical synthesis techniques that have traditionally been used with control/data-flow graphs as ForSyDe transformations. This approach avoids discontinuities as it moves design refinement into the domain of the specification model View full abstract»

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  • Visualisation and resolution of encoding conflicts in asynchronous circuit design

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    Synthesis of asynchronous circuits from signal transition graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. The refinement process is generally done automatically using heuristics. It often produces suboptimal solutions or sometimes fails to solve the problem. Thus manual intervention by the designer may be required. A framework is presented for an interactive refinement process aimed to help the designer. It is based on the visualisation of conflict cores, i.e. sets of transitions causing encoding conflicts, which are represented at the level of finite and complete prefixes of STG unfoldings View full abstract»

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  • Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

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    Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compilation tools are essential to their success. A modulo scheduling algorithm to exploit loop-level parallelism for coarse-grained reconfigurable architectures is presented. This algorithm is a key part of a dynamically reconfigurable embedded systems compiler (DRESC). It is capable of solving placement, scheduling and routing of operations simultaneously in a modulo-constrained 3D space and uses an abstract architecture representation to model a wide class of coarse-grained architectures. The experimental results show high performance and efficient resource utilisation on tested kernels View full abstract»

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  • Delay defect diagnosis based upon a statistical timing model-the first step

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    The problem of diagnosing delay defects is defined using a statistical timing model. The differences between delay defect diagnosis and traditional logic defect diagnosis are illustrated. Different diagnosis algorithms are proposed and their performance evaluated via statistical defect injection and statistical delay fault simulation. With a statistical timing analysis framework developed in the past, new concepts in delay defect diagnosis are demonstrated and experimental results are discussed based upon benchmark circuits View full abstract»

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  • Scheduling and mapping of conditional task graph for the synthesis of low power embedded systems

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    A dynamic voltage scaling (DVS) technique for embedded systems expressed as conditional task graphs (CTGs) is described. The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also the effect of combining a genetic algorithm based mapping with the DVS technique is examined and it is shown that further energy reduction can be achieved. The techniques are tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with an energy saving of up to 24%. Furthermore, it is shown that savings of up to 51% are achieved by considering DVS during the mapping optimisation. Finally, the impact of communications and communication link selection on the scheduling and mapping technique is investigated and results are reported View full abstract»

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  • Modelling and evaluation of substrate noise induced by interconnects

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    Interconnects have received attention as a source of crosstalk to other interconnects, but have been ignored as a source of substrate noise. The importance of interconnect-induced substrate noise is evaluated in this paper. A known interconnect and substrate model is validated by comparing simulation results to experimental measurements. Based on the validated modelling approach, a complete study considering frequency, geometrical, load and shielding effects is presented. The importance of interconnect-induced substrate noise is demonstrated after observing that, for typically sized interconnects and state-of-the-art speeds, the amount of coupled noise is already comparable to that injected by hundreds of transistors. The need to include high-frequency effects in the model is also discussed, together with accuracy trade-offs View full abstract»

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  • Dynamically increasing the scope of code motions during the high-level synthesis of digital circuits

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    The quality of high-level synthesis results for designs with complex and nested conditionals and loops can be improved significantly by employing speculative code motions. Two techniques are presented that add scheduling steps to the branch of a conditional construct with fewer scheduling steps. This 'balances' or equalises the number of scheduling steps in the conditional branches and increases the scope for application of speculative code motions. These branch balancing techniques have been applied 'dynamically' during scheduling. The authors have implemented algorithms for dynamic branch balancing techniques in a C-to-VHDL high-level synthesis framework called Spark. The utility of these techniques is demonstrated by experimental results on four designs derived from two moderately complex applications, namely, MPEG-1 and the GIMP image processing tool. These results show that the two branch balancing techniques can reduce the cycles on the longest path through the design by up to 38% and the number of states in the controller by up to 37% View full abstract»

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  • Editorial Date03

    Page(s): 253 - 254
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (209 KB)  

    First Page of the Article
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