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Electron Devices, IEEE Transactions on

Issue 7 • Date Jul 1991

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Displaying Results 1 - 17 of 17
  • Design aspects of MOS-controlled thyristor elements: technology, simulation, and experimental results

    Publication Year: 1991 , Page(s): 1605 - 1611
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    2.5-kV thyristor devices have been fabricated with integrated MOS controlled n+-emitter shorts and a bipolar turn-on gate using a p-channel DMOS technology. Square-cell geometries with pitch variations ranging from 15 to 30 μm were implemented in one- and two-dimensional arrays with up to 20000 units. The impact of the cell pitch on the turn-off performance and the on-state voltage was studied for arrays with constant cathode area as well as for single-cell structures. By realizing MOS components with submicrometer channel lengths, scaled single cells are shown to turn off with current densities of several kiloamperes per square centimeter at a gate bias of 5 V. In the case of multi-cell ensembles, turn-off performance is limited due to inhomogeneous current distribution. Critical process parameters as well as the device behavior were optimized through multidimensional numerical simulation View full abstract»

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  • Design and operation of a fully integrated BiC/DMOS head-actuator PIC for computer hard-disk drives

    Publication Year: 1991 , Page(s): 1590 - 1599
    Cited by:  Papers (4)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    A fully integrated head-actuator power integrated circuit (PIC) for computer hard-disk drives is described including a 1-A, 10-W CMOS H-bridge class-B amplifier. Operation of the complementary MOS-transistor power output stage includes a small-signal on-track mode and a five-interval high-speed large-signal seek mode. Analysis of a seek event reveals that maximum power dissipation occurs during the acceleration and deceleration intervals. Inductive flyback during break-before-make operation is clamped by integral multicollector bipolar transistors as confirmed by measurements and PISCES simulations. The mechanisms, occurrence, and device design considerations of the output transistor's flyback current partitioning into type A (source) and type B (Nwell) collector and base (body) current components are analyzed. The concept and implementation of a synchronous clamp are introduced. Finally, performance and parasitic suppression considerations of an advanced self-isolated BiC/DMOS process and device arsenal are discussed View full abstract»

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  • Analysis of CMOS-compatible lateral insulated base transistors

    Publication Year: 1991 , Page(s): 1624 - 1632
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (804 KB)  

    The authors describe the performance of various lateral insulated base transistors (LIBTs) fabricated with a 2.5-μm digital CMOS-compatible high-voltage integrated circuit (HVIC) process. Structural modifications have been proposed to the LIBTs reported to date, in order to improve their on-stage performance. The modifications have been achieved with the use of charge-controlled n+ buried layers incorporated within the device structures. These LIBTs are implemented with a novel HVIC process which is based on a 2.5-μm digital CMOS fabrication sequence. This process utilizes three additional steps carried out prior to the CMOS fabrication sequence. An important feature of this HVIC process is the use of a 400-Å gate oxide, which makes the power devices, fully compatible with the low-voltage digital circuits. During this work, a specific on-resistance of 0.016 Ω-cm2 and a turn-off delay of 90 ns have been obtained in an improved LIBT structure which is capable of withstanding up to 250 V View full abstract»

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  • Lateral MOS-gated power devices-a unified view

    Publication Year: 1991 , Page(s): 1600 - 1604
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    The authors present a unified view of lateral MOS-gated power devices based on the underlying device physics. This unified view facilities a qualitative understanding of the relative merit of different devices and their performance. Various MOS-controlled power and high-voltage devices can be viewed in a unified approach depending on the type of MOS gate control of the main current flowing through the device. The majority-carrier devices tend to favor speed over on-resistance. The mixed (bipolar-type) devices tend to favor lower on-resistance than speed. Hybrid devices are between these two extremes. Specifically, for high-frequency, high-voltage, and low-current applications the lateral DMOS (LDMOS) transistor is the device with the most desirable characteristics. At lower switching frequency and low-to-moderate current levels, the lateral IGBT (LIGBT) provides the same functionality with substantial areas savings. Lateral MOS-controlled thyristors (LMCTs) are suitable for low switching speed, high current applications View full abstract»

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  • An overview of smart power technology

    Publication Year: 1991 , Page(s): 1568 - 1575
    Cited by:  Papers (71)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    The evolution of smart power technology and the impact of this technology on electronic systems are reviewed. After providing a definition of smart power technology, the author describes the key technological developments in power semiconductor devices, namely power MOSFETs and IGBTs (insulated-gate bipolar transistors). These developments are the foundation upon which smart power technology rests. Smart power technology requires the marriage of power device technology with CMOS logic and bipolar analog circuits. The technical challenges involved in combining power handling capability with on-chip regulation of overcurrent, overvoltage, and overtemperature conditions are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies View full abstract»

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  • Analysis of negative differential resistance in the I-V characteristics of shorted-anode LIGBT's

    Publication Year: 1991 , Page(s): 1633 - 1640
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    The physical mechanism responsible for the negative differential resistance (NDR) in the current-voltage characteristics of the shorted anode lateral insulated gate bipolar transistor (SA-LIGBT) is explained through two-dimensional numerical simulation. The NDR regime is an inherent feature of all SA-LIGBTs, and results from the two different conduction mechanisms responsible for current flow in the device. These conduction mechanisms are minority-carrier injection and majority-carrier flow. Since both the anode geometry and the doping profile control the onset and the degree of minority-carrier injection, the effect these parameters have on the NDR is investigated. A simple lumped-element equivalent model of the SA-LIGBT allows qualitative predictions to be made on how changes in the device geometry and doping profiles influence the NDR regime. It is shown that conductivity modulation is a necessary but not sufficient condition for the occurrence of negative resistance in SA-LIGBT devices. Also required is a large voltage drop in the high-resistivity drift region before conductivity modulation is initiated. This causes small changes in the anode current level, greatly decreasing the total resistance across the drift region View full abstract»

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  • A surge-free intelligent power device specific to automotive high side switches

    Publication Year: 1991 , Page(s): 1576 - 1581
    Cited by:  Papers (9)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    A novel type of intelligent power device (IPD), which is suitable for automotive monolithic high side switch with high current capability, is presented. An integration of a vertical-power DMOSFET and planar MOS IC devices is performed by the newly developed junction-isolation technique using only one epitaxial growth. The isolation voltage of 80 V has been obtained, which is large enough for automotive IPDs if they are protected against high voltage transients on the battery line. A rugged vertical DMOSFET (VDMOS) has also been developed for this IPD. It has a cellular Zener diode between its source and drain, which prevents the secondary breakdown of parasitic bipolar transistor, and the resulting avalanche capability enhancement is more than an order of magnitude. This VDMOS is used for both output power device and protection device for low-voltage MOS circuitry, which makes the IPD free from any transients in the automobile without the need for external protection View full abstract»

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  • Analysis of n-channel MOS-controlled thyristors

    Publication Year: 1991 , Page(s): 1612 - 1618
    Cited by:  Papers (17)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    The turn-off of the n-channel MOS-controlled thyristor (NMCT) is analyzed using two-dimensional simulation. A lateral NMOS-controlled thyristor structure, LNMCT, suitable for HVIC application is also proposed. It is found that the operation of a parasitic lateral n-p-n transistor in NMCT-type structures degrades the forward voltage drop and the turn-off capability and hence should be suppressed. The maximum controllable current in the NMCT is not only a function of internal parameters, but also depends on external supply voltage. This indicates that snubberless operation of an MCT-type device is not feasible. The advantages and disadvantages of the NMCT are compared with those of conventional MCT structures. The LNMCT turn-off speed is limited by the large amount of holes existing in the substrate, resulting in a turn-off waveform similar to that of an LIGBT View full abstract»

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  • Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film

    Publication Year: 1991 , Page(s): 1650 - 1654
    Cited by:  Papers (39)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    Studies of high-voltage lateral device structures on a thin silicon layer over silicon dioxide have been carried out. It was found both theoretically and experimentally that over 600-V devices can be realized using a structure consisting of an n diffusion layer over a 15-μm-thick high-resistivity n- silicon layer over 3-μm silicon dioxide (SOI). A method is presented to enhance breakdown voltage by applying a large share of the voltage to the bottom oxide View full abstract»

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  • Optimization and surface charge sensitivity of high-voltage blocking structures with shallow junctions

    Publication Year: 1991 , Page(s): 1666 - 1675
    Cited by:  Papers (17)  |  Patents (34)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    The most commonly used high-voltage blocking and termination structures-floating field limiting rings (FLR), lateral charge control HVIC devices, and junction termination extension (JTE) structures-are very sensitive to positive silicon and silicon dioxide interface charges. These high-voltage termination structures specifically designed for 1000-V blocking capability lose 25 to 50% of their voltage-blocking capability under 5×1011 cm-2 net interface state density. In contrast, optimized multiple-zone JTE (MZ-JTE), and offset multiple field plated and field-limiting ring (OFP-FLR) structures will lose only 5% of their respective voltage blocking capabilities under the same surface-charge condition. These improved high-voltage blocking structures do not require additional passivation and process complexities View full abstract»

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  • A versatile 700-1200-V IC process for analog and switching applications

    Publication Year: 1991 , Page(s): 1582 - 1589
    Cited by:  Papers (25)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (912 KB)  

    An IC process with a wide range of devices up to 1200 V is described. In addition to low-voltage bipolars and CMOS and 230-V VDMOS it provides 700-V high-side LDMOS, HV-PMOS (EPMOS) and low-voltage circuitry, low-side 1200-V LDMOS and 700-V LIGBT (lateral insulated-gate bipolar transistor), as well as 700-V interconnection. These features have been realized by using a substrate of higher resistance in a 250-300-V IC process and by adaptation in the Resurf structure for lateral DMOS. Application examples for flyback and half-bridge power conversion and as a power-bridge driver are given View full abstract»

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  • High-voltage planar devices using field plate and semi-resistive layers

    Publication Year: 1991 , Page(s): 1681 - 1684
    Cited by:  Papers (26)  |  Patents (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    An improved high-voltage technique based on the use of a field plate combined with semiresistive layers (SIPOS) on oxide is proposed. The field plate and SIPOS (semi-insulating polycrystalline silicon) are shown to have complementary functions. Junction curvature electric field effects are reduced by the presence of the field plate. The silicon surface potential is linearized by a primary SIPOS layer on oxide, thereby reducing the peak electric field at the edge of the field plate. A second high-resistivity SIPOS layer provides an excellent passivation, and also prevents the dielectric breakdown of the underlayer SIPOS film. Moreover, the savings in chip area is about 20% compared to the standard mesa termination. The global yield is 94% for the SIPOS planar transistors and 86% for equivalent devices in mesa technology. The complete fabrication, design, electrical characteristics, and reliability of high-voltage planar transistors are described View full abstract»

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  • Quasi-dielectrically isolated bipolar junction transistor with subcollector fabricated using silicon selective epitaxy

    Publication Year: 1991 , Page(s): 1660 - 1665
    Cited by:  Papers (5)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    A novel quasi-dielectrically isolated bipolar junction transistor (QDI-BJT) was developed for intelligent power ICs. Using a combination of junction and dielectric isolation, the QDI-BJT was achieved by selective epitaxial growth (SEG) of single-crystal silicon in an oxide-lined trench. Buried collectors formed by ion implantation and in situ doped SEG silicon drastically reduce collector resistance with no detrimental effects on transistor performance. The emitter-base and collector-base ideality factors at 1.10 and 1.09, respectively, were very close to those of similar devices fabricated in the substrate in the same die, indicating excellent crystal quality of the SEG silicon. Due to the use of a trench structure to facilitate isolation and control the SEG thickness, the QDI process can be used for any application where the thickness and resistivity of the control and power areas are independently optimized View full abstract»

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  • New physical insights and models for high-voltage LDMOST IC CAD

    Publication Year: 1991 , Page(s): 1641 - 1649
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    The lateral DMOST (LDMOST), including an LDD (lightly doped drain) and the inherent BJT (bipolar junction transistor), is studied extensively using the two-dimensional device simulator PISCES. The PISCES simulations provide physical insights into the normal- and reverse-mode operations of the LDMOST, which are used for developing a comprehensive LDD LDMOST model for circuit simulation. In the modeling methodology, the LDD LDMOST is regionally partitioned into three main components (the channel, the drift region, and the BJT), and carrier-transport problems in each component are solved. The composite physical model is implemented in SPICE for HVIC (high-voltage integrated circuit) CAD and is supported by measurements. The modeling methodology is also applicable to the Resurf LDMOST View full abstract»

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  • A 100-V lateral DMOS transistor with a 0.3-micrometer channel in a 1-micrometer silicon-film-on-insulator-on-silicon

    Publication Year: 1991 , Page(s): 1655 - 1659
    Cited by:  Papers (11)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB)  

    A novel LDMOS transistor structure with breakdown voltages above 100 V has been fabricated in silicon-on-insulator-on-silicon (SOIS). This structure has been fabrication by silicon direct bonding (SDB) and etch-back to a typical film thickness of 1 μm. The silicon carrier layer (handle) serves as a back-gate electrode, which, under proper bias, improves the transistor characteristics significantly. The effective channel length or basewidth is 0.3 μm. Under these conditions, the drift region becomes the current-limiting element. The physics in the drift region in thin silicon films (⩽1 μm) in the transistor on-state is dominated by the injected electrons from the channel. The limitation of the maximum drain current is given by the quasi-saturation effect. Criteria for the further optimization of SOIS LDMOS transistors are presented View full abstract»

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  • Breakdown voltage in LDMOS transistors using internal field rings

    Publication Year: 1991 , Page(s): 1676 - 1680
    Cited by:  Papers (9)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    The optimization of the floating-ring parameters and the breakdown voltage of a lateral DMOS (LDMOS) transistor using a single floating ring is presented. A first-order analytical approach is presented, showing the upper limit of the position of the ring, with respect to the channel, and the doping concentration within the ring to increase the breakdown voltage. A 2D numerical calculation of the breakdown voltage and on-resistance of the LDMOS transistor is also presented. The results, which support the analytical approach, allow the use of simple design rules for the implementation of high-voltage LDMOS transistors on a thick epitaxial layer. It is shown that improvements of breakdown voltage is obtained if the distance between the channel and the field ring is equal to the field plate length and the doping concentration in the ring satisfies a specific relationship. With a single ring, the breakdown voltage increases from 170 to 280 V for the same device area and to over 480 V if the area is allowed to increase by 25% View full abstract»

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  • Characteristics of the emitter-switched thyristor

    Publication Year: 1991 , Page(s): 1619 - 1623
    Cited by:  Papers (37)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    The first experimental demonstration of 600-V emitter-switched thyristors fabricated using an IGBT (insulated-gate bipolar transistor) process sequence is reported. The forward drop is less than that for the IGBT, but larger than that for a thyristor by about 0.5 V due to the thyristor current flowing via the MOSFET channel. A unique characteristic observed for these devices, not exhibited by any previous MOS-gated thyristor structures, is gate-controlled current saturation even after thyristor latch-up. Switching tests were performed up to a current density of 1000 A/cm2 on single-unit cells and the measured turn-off times were about 7 μs View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

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University of California San Diego