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Electron Devices, IEEE Transactions on

Issue 11 • Date Nov. 2003

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Displaying Results 1 - 19 of 19
  • Current mismatch due to local dopant fluctuations in MOSFET channel

    Page(s): 2248 - 2254
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (619 KB)  

    A microscopic multitransistor model is developed to analyze the impact of local dopant fluctuation on the intrinsic mismatch of long-channel MOSFET. A closed analytical formula for current mismatch is derived to show a nonscaled and self-consistent form ∼[4+Log(L/Lmin)]/WL. This is in contrast to the global fluctuation model, in which the current mismatch has a universal scaling form ∼1/WL but is not self-consistent if a MOSFET is modeled as an equivalent two-transistor system. The weak violation of scaling law results from the local fluctuation that has more impact on longer channel devices than on shorter ones. Our new model is consistent with recent experimental observation and can explain the discrepancies between the experimental data and the existing models. The analysis indicates that the local dopant fluctuation is the major cause and accounts for about 60% to 80% of total current mismatch when operated at lower gate voltage, a usual regime for higher output impedance. View full abstract»

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  • Sensitivity of double-gate and FinFETDevices to process variations

    Page(s): 2255 - 2261
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (441 KB)  

    We investigate the manufacturability of 20-nm double-gate and FinFET devices in integrated circuits by projecting process tolerances. Two important factors affecting the sensitivity of device electrical parameters to physical variations were quantitatively considered. The quantum effect was computed using the density gradient method and the sensitivity of threshold voltage to random dopant fluctuation was studied by Monte Carlo simulation. Our results show the 3σ value of VT variation caused by discrete impurity fluctuation can be greater than 100%. Thus, engineering the work function of gate materials and maintaining a nearly intrinsic channel is more desirable. Based on a design with an intrinsic channel and ideal gate work function, we analyzed the sensitivity of device electrical parameters to several important physical fluctuations such as the variations in gate length, body thickness, and gate dielectric thickness. We found that quantum effects have great impact on the performance of devices. As a result, the device electrical behavior is sensitive to small variations of body thickness. The effect dominates over the effects produced by other physical fluctuations. To achieve a relative variation of electrical parameters comparable to present practice in industry, we face a challenge of fin width control (less than ∼1 nm 3σ value of variation) for the 20-nm FinFET devices. The constraint of the gate length variation is about 10∼15%. We estimate a tolerance of 1∼2 Å 3σ value of oxide thickness variation and up to 30% front-back oxide thickness mismatch. View full abstract»

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  • Simulating program disturb faults in flash memories using SPICE compatible electrical model

    Page(s): 2286 - 2291
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (365 KB) |  | HTML iconHTML  

    Electrical simulation is an important tool that enables designers to evaluate different design alternatives and assess their performance. In memory technology, these tools are used to study the performance of different cell structures and implementations. In this paper we use such simulations to study the impact of defects on the performance of flash memory bitcells. In particular, using a device level simulator, we develop a SPICE compatible model to simulate the operation of a 1T flash bitcell. We then describe a fault injection technique that can be used, in conjunction with the model, to simulate faulty cell behavior. The model is used to simulate different defects in the oxide layer of the flash core memory element. The impact of defects on bitcell behavior under disturb and normal operations is investigated and evaluated. The model is demonstrated to be valuable to evaluate the appropriateness of the logic tests and stress tests used to detect such defects in flash memories. View full abstract»

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  • The thermal stability of one-transistor ferroelectric memory with Pt-Pb5Ge3O11-Ir-poly-SiO2-Si gate stack

    Page(s): 2280 - 2285
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (461 KB) |  | HTML iconHTML  

    The thermal stability of one-transistor ferroelectric nonvolatile memory devices with a gate stack of Pt-Pb5Ge3O11-Ir-Poly-SiO2-Si was characterized in the temperature range of -10°C to 150°C. The memory windows decrease when the temperatures are higher than 60°C. The drain currents (ID) after programming to on state decrease with increasing temperature. The drain currents (ID) after programming to off state increase with increasing temperature. The ratio of drain current (ID) at on state to that at off state drops from 7.5 orders of magnitude to 3.5 orders of magnitude when the temperature increases from room temperature to 150°C. On the other hand, the memory window and the ratio of ID(on)/ID(off) of the one-transistor memory device displays practically no change when the temperature is reduced from room temperature to -10°C. One-transistor (1T) memory devices also show excellent thermal imprint properties. Retention properties of 1T memory devices degrade with increasing temperature over 60°C. View full abstract»

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  • Quasi-static and nonquasi-static compact MOSFET models based on symmetric linearization of the bulk and inversion charges

    Page(s): 2262 - 2272
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (830 KB) |  | HTML iconHTML  

    A particularly simple form of the charge-sheet model (CSM) is developed using symmetric linearization of the bulk charge as a function of the surface potential. The new formulation is verified by comparison with the original form of the CSM and is used to obtain a simple and accurate expressions for the quasi-static (QS) terminal charges based on the Ward-Dutton partition. Combined with the spline collocation version of the weighted residuals method, symmetric linearization leads to a relatively simple version of the nonquasi-static (NQS) MOSFET model. The efficiency of the proposed approach to MOSFET modeling is enhanced by taking advantage of the recently developed noniterative algorithm for computing surface potential as a function of the terminal voltages. An important symmetry of the various MOSFET characteristics with respect to the source/drain interchange is preserved in both the QS and NQS versions of the symmetrically linearized CSM. View full abstract»

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  • A novel bipolar imaging device - BASIC (BAse stored imager in CMOS Process)

    Page(s): 2189 - 2195
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (569 KB) |  | HTML iconHTML  

    A new pixel structure named base stored imager in CMOS process (BASIC), is proposed and realized with a conventional 1.5 μm CMOS process. The BASIC cell comprises three pMOSFETs and a new photosensor, which has the gate-body tied nMOSFET structure. The BASIC cell achieves high responsivity because the photosensor amplifies the photogenerated electron-hole pairs. Dynamic range is improved by using the reset of the base through the pMOSFET and correlated double sampling operation. The structure and operation principles of the BASIC cell are presented together with measurement results from the fabricated samples. It is shown that the BASIC cell can be scaled down for large arrays and it is adequate for low voltage operation. View full abstract»

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  • An improved method to estimate intrinsic small signal parameters of a GaAs MESFET from measured dc characteristics

    Page(s): 2196 - 2201
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (453 KB) |  | HTML iconHTML  

    This investigation offers a technique to predict the ac behavior of mm wavelength GaAs metal semiconductor field effect transistors by using dc characteristics. To predict the intrinsic equivalent circuit parameters of the device from dc data, the measured dc characteristics are first simulated by employing a nonlinear dc model. The effects of biasing on the device ac parameters are evaluated for its low-noise applications. An improvement greater than 10% in predicting the ac response of the device is observed. The concept of depletion layer modification caused by the transverse electric field inside the channel is introduced for accurate Miller's capacitor modeling. It is assumed that with increased device biasing there are more unbalanced positive charges in the gate depletion toward the drain-side of the Schottky barrier. The electric field lines originated by these uncompensated charges induce an opposite charge density in the gate electrode. This modifies the gate biasing and hence the Schottky barrier depletion. As a result, the values of intrinsic ac device parameters change. It is observed that an accurate dc modeling is key to predicting an accurate ac small signal equivalent circuit of a device. View full abstract»

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  • An insulated shallow extension structure for bulk MOSFET

    Page(s): 2294 - 2297
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    This brief proposes possible a replacement of shallow p-n junction with insulated shallow extension (ISE) structure for bulk MOSFET. The shallow extension is defined by the sidewall thermal oxide rather than the implanted p-n junction. With this insulator for extension and main junction, a heavier halo doping concentration can be used. Thus, the threshold-voltage roll-off and the junction leakage current can be minimized simultaneously. This structure can be a good alternative for junction structures in sub-100-nm regimes. View full abstract»

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  • Simultaneous quality improvement of tunneling- and interpoly-oxides of nonvolatile memory devices by NH3 and N2O nitridation

    Page(s): 2300 - 2302
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (331 KB) |  | HTML iconHTML  

    This brief presents a new nitridation process on a floating poly-Si gate to improve the quality of both tunneling oxide and interpoly-oxide of nonvolatile memories. Three types of poly-Si for a floating gate have been investigated. We found in-situ doped poly-Si shows the best performance in terms of breakdown field, charge-to-breakdown (QBD) and trapping rate. The QBD of interpoly-oxide can be reached as high as 35 C/cm2. This scheme is very promising for nonvolatile memory devices. View full abstract»

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  • Comparison of zincblende-phase GaN, cubic-phase SiC, and GaAs MESFETs using a full-band Monte Carlo Simulator

    Page(s): 2202 - 2207
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    We present a theoretical study of metal-semiconductor field-effect transistor (MESFET) devices for three different materials: zincblende-phase gallium nitride (ZB-GaN), cubic-phase silicon carbide (3C-SiC) and gallium arsenide (GaAs). The dc breakdown voltage of comparable MESFETs made with the two wide bandgap materials, ZB-GaN and 3C-SiC are compared to that made with the well studied material, GaAs. In this way, the GaAs calculations serve as a control, enabling an accurate comparison of the device behaviors. The simulations are performed with a new, generalized, self-consistent, full-band Monte Carlo simulator. The new simulator includes fully numerical scattering rates and a fully numerical, overlap-based final-state selection process. A 0.1 μm gate-length MESFET is used for all of the simulations, and rectangular wells of lightly doped material are used to model interface states. The calculated dc breakdown voltages of the ZB-GaN, 3C-SiC, and GaAs MESFETs are 18, 16, and 5 V respectively. The previously estimated factor-of-four difference between the breakdown voltage of ZB-GaN and GaAs devices is verified. View full abstract»

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  • Measurements and extractions of parasitic capacitances in ULSI layouts

    Page(s): 2236 - 2247
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (838 KB)  

    This paper deals with the extraction of parasitic capacitances of interconnects in submicron layouts. It is well known that, in integrated circuits, the signal delay due to interconnects is comparable to that of gates. This aspect becomes particularly important, for example, during the design of clock trees in high-speed applications. In general, capacitance extraction is carried out with software tools but they should be validated on a set of geometrical structures, which have been accurately characterized and that are representative of the circuit layouts. Experimental characterization of these structures and their set up in a golden set of measures is still a challenging task. In this paper, we first describe some experimental approaches to measure capacitances of structures from the golden set and in particular we identify a high accuracy transducer based on pass-gate transistors. We then propose a software implementation of the floating random walk algorithm that solves the drawbacks in the extraction of capacitances of interconnects in a nonhomogeneous medium as an industrial layout. Finally, experimental and simulation results are presented, validating the adopted approach. View full abstract»

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  • A general design methodology for the optimal multiple-field-limiting-ring structure using device simulator

    Page(s): 2273 - 2279
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (597 KB) |  | HTML iconHTML  

    A design methodology for the optimal multiple-field-limiting-ring (FLR) termination structure is proposed. In the methodology, a simple modeling structure is developed to find the so-called BV-spacing curve, from which the optimal structure can be obtained directly without trial and error. The results given by the methodology is in excellent agreement with the experimental results. The applicability of the methodology is also investigated in a wide scope, which shows that the methodology has a very good performance in the medium-voltage-range FLR termination design. View full abstract»

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  • Improvement of charge-to-breakdown distribution by fluorine incorporation into thin gate oxides

    Page(s): 2221 - 2226
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB) |  | HTML iconHTML  

    This paper reports on the effect of fluorine incorporation on gate-oxide reliability, especially the spatial distribution of charge-to-breakdown (QBD). Fluorine atoms were implanted into gate electrodes and introduced into gate-oxide films by annealing. Excess fluorine incorporation increased the oxide thickness and degraded not only the reliability of Si/SiO2 interfaces but also dielectric-breakdown immunity. However, it was found, for the first time, that appropriate fluorine incorporation into gate-oxide films could dramatically improve QBD-distribution tails in Weibull plots, while maintaining both Si/SiO2 interface characteristics and average QBD values. The experimental result for a depth profile of fluorine atoms indicated that fluorine atoms are located dominantly at the two interfaces of the gate-oxide film. In addition, the results of infrared (IR) absorption analysis indicated that the strain of SiO2 structures is reduced with increasing fluorine doses. We proposed that both strain release and restructuring of the SiO2 network by fluorine incorporation are responsible for improving the QBD of weaker oxide films. View full abstract»

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  • Monte Carlo simulations of the bandwidth of InAlAs avalanche photodiodes

    Page(s): 2291 - 2294
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (393 KB) |  | HTML iconHTML  

    We present a Monte Carlo simulation of the bandwidth of an InAlAs avalanche photodiode with an undepleted absorber. The carrier velocities are simulated in the charge layer and the multiplication region. It is shown that the velocity overshoot effect is not as significant as simpler models have suggested. At high electric field intensity, the electron effective saturation velocity is only slightly higher when impact ionization is significant, compared with when impact ionization is absent. The simulated 3 dB bandwidth is consistent with experiments for gains up to 50. View full abstract»

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  • A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application

    Page(s): 2297 - 2299
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (353 KB) |  | HTML iconHTML  

    In this brief, a self-aligned electrically separable double-gate (SA ESDG) MOS transistor technology is proposed and demonstrated. The SA ESDG structure is implemented by defining a dummy top gate that is self-aligned to the bottom gate and then later replacing the dummy using a real top gate. The proposed process is applied to the single-grain Si film formed by recrystallizing a low-pressure chemical vapor deposition a-Si with a metal induced unilateral crystallization technique and enhancing the grain sizes in a subsequent high temperature annealing step. The ideal device structure resulting from the process is verified by scanning electron microscope imaging. The good current-voltage characteristics and the noticeable dynamic threshold voltage effects are also observed in the implemented SA ESDG device. View full abstract»

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  • Design guideline for minimum channel length in silicon-on-insulator (SOI) MOSFET

    Page(s): 2303 - 2305
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (339 KB) |  | HTML iconHTML  

    This brief proposes a preliminary design guideline for the minimum channel length in silicon-on-insulator (SOI) MOSFETs that is based on simulations of device characteristics. The simulations examine a wide variation in many device parameters to comprehensively evaluate device characteristics. A characteristic parameter that can successfully describe the minimum channel length is found. It is suggested that a sub-20-nm-channel single-gate SOI MOSFET with suppressed short-channel effects can be stably realized by optimizing its device parameters. View full abstract»

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  • High brightness InGaN green LEDs with an ITO on n++-SPS upper contact

    Page(s): 2208 - 2212
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    Indium tin oxide (ITO) (260 nm) and Ni (5 nm)/Au (10 nm) films were deposited onto glass substrates, p-GaN layers, n+-InGaN/GaN short-period-superlattice (SPS), n++-SPS and nitride-based green light-emitting diodes (LEDs). It was found that ITO could provide us an extremely high transparency (i.e., 95% at 520 nm). It was also found that the 1.03×10-3 Ωcm2 specific contact resistance of ITO on n++-SPS was reasonably small. Although the forward voltage of the LED with ITO on n++-SPS upper contacts was slightly higher than that of the LED with Ni/Au on n++-SPS upper contacts, the 20 mA output power and external quantum efficiency of the former could reach 4.98 mW and 8.2%, respectively, which were much larger than the values observed from the latter. The reliability of ITO on n++-SPS upper contacts was also found to be reasonably good. View full abstract»

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  • Above-threshold parameter extraction and modeling for amorphous silicon thin-film transistors

    Page(s): 2227 - 2235
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    This paper presents modeling and parameter extraction of the above-threshold characteristics of hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) in both linear and saturation regions of operation. A bias- and geometry-independent definition for field effect mobility considering the ratio of free-to-trapped carriers is introduced, which conveys the properties of the active semiconducting layer. A method for extraction of model parameters such as threshold voltage, effective mobility, band-tail slope, and contact resistance from the measurement results is presented. This not only provides insight to the device properties, which are highly fabrication-dependent, but also enables accurate and reliable TFT circuit simulation. The techniques presented here form the basis for extraction of physical parameters for other TFTs with similar gap properties, such as organic and polymer TFTs. View full abstract»

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  • High-performance self-aligned SiGeC HBT with selectively grown Si1-x-yGexCy base by UHV/CVD

    Page(s): 2213 - 2220
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (721 KB) |  | HTML iconHTML  

    Si1-x-yGexCy selective epitaxial growth (SEG) was performed by cold-wall, ultrahigh-vacuum chemical vapor deposition, and the effects of incorporating C on the crystallinity of Si1-x-yGexCy layers and the performance of a self-aligned SiGeC heterojunction bipolar transistor (HBT) were evaluated. A Si1-x-yGexCy layer with good crystallinity was obtained by optimizing the growth conditions. Device performance was significantly improved by incorporating C, as a result of applying Si1-x-yGexCy SEG to form the base of a self-aligned HBT. Fluctuations in device performance were suppressed by alleviating the lattice strain. Furthermore, since the B out diffusion could be suppressed by incorporating C, the cutoff frequency was able to be increased with almost the same base resistance. A maximum oscillation frequency of 174 GHz and an emitter coupled logic gate-delay time of 5.65 ps were obtained at a C content of 0.4%, which shows promise for future ultrahigh-speed communication systems. View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego