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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 5 • Date Oct. 2003

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Guest editorial

VTCMOS characteristics and its optimum conditions predicted by a compact analytical model

Voltage-pulse driven harmonic resonant rail drivers for low-power applications

Optimization of scannable latches for low energy

Energy-efficient issue queue design

Micro-operation cache: a power aware frontend for variable instruction length ISA

Application-directed voltage scaling

Adaptive low-power address encoding techniques using self-organizing lists

A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters

Test data compression and test time reduction using an embedded microprocessor

Multiple-parameter CMOS IC testing with increased sensitivity for I/sub DDQ/

A digitally programmable delay element: design and analysis

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

Improved model-order reduction by using spacial information in moments

Modeling technology impact on cluster microprocessor performance

Petri net modeling of gate and interconnect delays for power estimation

Memory allocation and mapping in high-level synthesis - an integrated approach

A high-speed energy-efficient 64-bit reconfigurable binary adder

A dictionary-based en/decoding scheme for low-power data buses

Reduction of coupling effects by optimizing the 3-D configuration of the routing grid

Design of reconfigurable access wrappers for embedded core based SoC test

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