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IEEE Design & Test of Computers

Issue 3 • Sept. 1991

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Displaying Results 1 - 6 of 6
  • System complexity and integrated diagnostics

    Publication Year: 1991, Page(s):16 - 30
    Cited by:  Papers (24)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1478 KB)

    An overview of a complete approach to integrated diagnostics is given. The approach is centered around an information-flow model and incorporates techniques from information fusion and artificial intelligence to guide analyses. The concept of integrated diagnosis is explained, and the model is examined. The authors show how to analyze testability, evaluate fault diagnosis, and create maintenance a... View full abstract»

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  • Designing in power-down test circuits

    Publication Year: 1991, Page(s):31 - 35
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Built-in self-test circuitry that is active only during testing is described. The benefit of these types of circuits is that defects that are not uncovered within the test circuitry will not contribute to failures in the host's ICs. Thus, the overall reliability of the IC in its targeted application should increase. Also, since the test circuitry is inactive, there will be less overall power consu... View full abstract»

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  • Electrical characterization of megabit DRAMs. 1. External testing

    Publication Year: 1991, Page(s):36 - 43
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (789 KB)

    An approach to the electrical characterization of dynamic RAMs in which chip design and DRAM process technology are verified and optimized concurrently is reported. Both parametric and functional tests were performed. The authors describe an information and scheduling system for analysis and testing that handles the required electrical measuring data from the testers. It is shown how data analysis... View full abstract»

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  • Increasing test accuracy by varying driver slew rate

    Publication Year: 1991, Page(s):44 - 48
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (483 KB)

    A variable slew rate, together with the ability to control ascending and descending slew rates independently, significantly improves the overall accuracy of test and verification systems for application-specific ICs. Although a high slew rate is usually desirable, in some cases, such as ECL devices and devices in circuits of older vintage, a variable rate is advantageous. Essential driver characte... View full abstract»

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  • Reorganizing circuits to aid testability

    Publication Year: 1991, Page(s):49 - 57
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    A method of partitioning a circuit canonically into disjoint subcircuits and to group similarly connected storage elements is described. The method is being used in a program called Crete (for Clouding, hierarchical Reorganization, Equivalence determination, Test-methodology embedding, and Editing). Crete partitions and reorganizes the hierarchical description of a circuit so that the designer can... View full abstract»

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  • Pseudorandom testing for boundary-scan design with built-in self-test

    Publication Year: 1991, Page(s):58 - 65
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (679 KB)

    The design of a pseudorandom pattern generator for a boundary-scan chip with built-in self-test is described. The proposed test-generation procedure, together with a method of connecting the generator outputs and the primary inputs of the chip under test, ensures full pattern coverage. The authors show how to evaluate the choice of generator parameters and initial states when there are more flip-f... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

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Editor-in-Chief
Krishnendu Chakrabarty