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Electron Device Letters, IEEE

Issue 9 • Date Sept. 2003

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Displaying Results 1 - 25 of 26
  • 40-Gbit/s OEIC on GaAs substrate through metamorphic buffer technology

    Page(s): 529 - 531
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (289 KB) |  | HTML iconHTML  

    An optoelectronic integrated circuit operating in the 1.55-μm wavelength range was realized on GaAs substrate through metamorphic technology. High indium content layers, metamorphically grown on a GaAs substrate, were used to fabricate the optoelectronic integrated circuits (OEICs) with -3 dB bandwidth of 40 GHz and 210 V/W of calculated responsivity. The analog OEIC photoreceiver consists of a 12-μm, top-illuminated p-i-n photodiode, and a traveling wave amplifier (TWA). This receiver shows 6 GHz wider bandwidth than a hybrid photoreceiver, which was built using comparable, but stand-alone metamorphic p-i-n diode and TWA. With the addition of a buffer amplifier, the OEIC shows 7 dB more gain than the hybrid counterpart. To our knowledge, this is the first 40 Gbit/s OEIC achieved on a GaAs substrate operating at 1.55 μm. View full abstract»

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  • Metal-semiconductor-metal photodetectors with InAlGaP capping and buffer layers

    Page(s): 532 - 534
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (238 KB) |  | HTML iconHTML  

    To improve the Schottky contact performance and carrier confinement of GaAs metal-semiconductor-metal photodetectors (MSM-PDs), we employed the wide bandgap material, In/sub 0.5/(Al/sub 0.66/Ga/sub 0.34/)/sub 0.5/P, for the capping and buffer layers. We directly evaluated the Schottky contact parameters on the MSM-PD structure. The reverse characteristics of the Schottky contacts were examined by taking into account the Schottky barrier height depended on the electric field in the depletion region, and hence on the applied bias. The ideality factor and Schottky barrier height of Ti-Pt-Au contacts to In/sub 0.5/(Al/sub 0.66/Ga/sub 0.34/)/sub 0.5/P are 1.02 and 1.05 eV, respectively. Extremely low dark currents of 70 and 620 pA were obtained for these MSM-PDs when they were operated at a reverse bias of -10 V at room temperature and at 70/spl deg/C, respectively. View full abstract»

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  • Effect of the surface and barrier defects on the AlGaN/GaN HEMT low-frequency noise performance

    Page(s): 535 - 537
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (250 KB) |  | HTML iconHTML  

    We report on the effect of Si/sub 3/N/sub 4/ passivation of the surface of AlGaN/GaN transistors on low-frequency noise performance. Low-frequency noise measurements were performed on the device before and after the passivation by a Si/sub 3/N/sub 4/ film. A lower level of the low-frequency noise was observed from the device after the passivation. The passivation layer improved high-frequency, large-signal device performance, but introduced parasitic leakage current from the gate. A lower level of flicker noise is explained by the fact that noise is mostly originated from the fluctuation of sheet charge and mobility in the ungated region of the device due to the defects on the surface and in the barrier of the unpassivated device. Passivation eliminates part of the defects and higher leakage current increases the number of electrons on the surface and in the vicinity of the barrier defects, lowering the contribution to the low-frequency noise according to Hooge's law. View full abstract»

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  • 0.6-eV bandgap In/sub 0.69/Ga/sub 0.31/As thermophotovoltaic devices grown on InAs/sub y/P/sub 1-y/ step-graded buffers by molecular beam epitaxy

    Page(s): 538 - 540
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (534 KB) |  | HTML iconHTML  

    Single-junction, lattice-mismatched (LMM) In/sub 0.69/Ga/sub 0.31/As thermophotovoltaic (TPV) devices with bandgaps of 0.60 eV were grown on InP substrates by solid-source molecular beam epitaxy (MBE). Step-graded InAs/sub y/P/sub 1-y/ buffer layers with a total thickness of 1.6 μm were used to mitigate the effects of 1.1% lattice mismatch between the device layer and the InP substrate. High-performance single-junction devices were achieved, with an open-circuit voltage of 0.357 V and a fill factor of 68.1% measured at a short-circuit current density of 1.18 A/cm2 under high-intensity, low emissivity white light illumination. Device performance uniformity was outstanding, measuring to better than 1.0% across a 2-in diameter InP wafer indicating the promise of MBE growth for large area TPV device arrays. View full abstract»

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  • Submicron gate Si3N4/AlGaN/GaN-metal-insulator-semiconductor heterostructure field-effect transistors

    Page(s): 541 - 543
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (250 KB) |  | HTML iconHTML  

    We present the characteristics of a quarter-micron gate metal-insulator-semiconductor heterostructure field-effect transistor (MISHFET) with Si/sub 3/N/sub 4/ film as a gate insulator. A detailed comparison of the MISHFET and an identical geometry HFET shows them to have the same radio frequency (RF) power gain and cut-off frequency, while the MISHFET has much lower gate-leakage currents and higher RF powers at operating frequencies as high as 26 GHz. The MISHFET gate-leakage currents are well below 100 pA at gate bias values from -10 V to +8 V. At zero gate bias, the drain saturation current is about 0.9 A/mm and it increases to 1.2 A/mm at +8 V gate bias. The output RF power of around 6 W/mm at 40 drain bias was found to be frequency independent in the range of 2 to 26 GHz. This power is 3 dB higher than that from HFET of the same geometry. The intrinsic cutoff frequency is /spl sim/63 GHz for both the HFET and the MISHFET. This corresponds to an average effective electron velocity in the MISHFET channel of 9.9/spl times/10/sup 6/ cm/s. The knee voltage and current saturation mechanisms in submicron MISHFETs and heterostructure field-effect transistors (HFET) are also discussed. View full abstract»

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  • Study of nickel silicide contact on Si/Si1-xGex

    Page(s): 544 - 546
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1001 KB) |  | HTML iconHTML  

    The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer. View full abstract»

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  • A low-temperature metal-doping technique for engineering the gate electrode of replacement metal gate CMOS transistors

    Page(s): 547 - 549
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    This work describes a low-temperature metal annealing technique that can be a helpful tool for fabricating the gate electrode of replacement metal gate CMOS transistors. The goal of the technique is to form doped metal (TaSiN, TiSiN, TaCN, TaPN, etc.) to change the work function of the metal gate electrode. The low-temperature doping process was performed in an ambient containing the precursors of the dopants, including silane, phosphine, and carbon-rich organic precursors. Experiments have been conducted to incorporate dopants such as P, C, Si into TaN or TiN. The transistor and C-V data show the resultant doped metals are suitable materials for P- and N-MOSFETs by providing the right metal work function. View full abstract»

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  • On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices

    Page(s): 550 - 552
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    The work function of ALD TiN was found to be above 5 eV after RTP annealing below 800/spl deg/C in a nitrogen atmosphere, while higher annealing temperatures cause a drop in work function by about 0.3-0.5 eV. The effect was found for TiN metal gates on both SiO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics in MOS-capacitors and was seen in C-V as well as in I-V measurements. On the contrary, annealing of SiO/sub 2/ capacitors in oxygen-enriched N/sub 2/ atmosphere increased the work function. A variation in EOT of less than 2 A was demonstrated for the various annealing temperatures, concluding that the ALD TiN is stable in contact with the different dielectric materials. However, the decrease in work function that is found in this investigation may implicate that ALD TiN is less suitable as a metal gate for pMOSFETs. View full abstract»

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  • High-performance Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure for nondestructive readout memory

    Page(s): 553 - 555
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (397 KB) |  | HTML iconHTML  

    Metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with 390-nm-thick SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) ferroelectric film and 8-nm-thick hafnium oxide (HfO/sub 2/) layer on silicon substrate have been fabricated and characterized. It is demonstrated for the first time that the MFIS stack exhibits a large memory window of around 1.08 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 18% degradation in the memory window after 10/sup 9/ switching cycles. The excellent performance is attributed to the formation of well-crystallized SBT perovskite thin film on top of the HfO/sub 2/ buffer layer, as evidenced by the distinctive sharp peaks in X-ray diffraction (XRD) spectra. In addition to its relatively high /spl kappa/ value, HfO/sub 2/ also serves as a good seed layer for SBT crystallization, making the proposed Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure ideally suitable for low-voltage and high-performance ferroelectric memories. View full abstract»

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  • MOS characteristics of ultrathin CVD HfAlO gate dielectrics

    Page(s): 556 - 558
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    Thermally stable, high-quality ultrathin (EOT=13 A) CVD HfAlO gate dielectrics with poly-Si gate electrode have been investigated for the first time. Results demonstrate that while in situ doping with Al significantly increases the crystallization temperature of HfO/sub 2/ up to 900/spl deg/C and improves its thermal stability, it also introduces negative fixed oxide charges due to Al accumulation at the HfAlO-Si interface, resulting in mobility degradation. The effects of Al concentration on crystallization temperature, fixed oxide charge density, and mobility degradation in HfAlO have been characterized and correlated. View full abstract»

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  • Physical models for predicting plasma nitrided Si-O-N gate dielectric properties from physical metrology

    Page(s): 559 - 561
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (286 KB) |  | HTML iconHTML  

    Using simple physical models, specific relationships between parameters measured by X-ray photoelectron spectroscopy (XPS) and those measured on MOS transistors are described for silicon oxynitride gate dielectrics prepared by plasma nitridation. Correlations are established between the equivalent oxide thickness (EOT) and gate leakage current and the nitrogen anneal dose and physical thickness as measured by XPS. These correlations, from devices in the 10 to 13 /spl Aring/ EOT range, allow accurate estimates of electrical thickness and leakage without device fabrication, enabling both development and process monitoring for sub-130-nm node gate dielectrics. View full abstract»

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  • Dielectric resolution enhancement coating technology (DiRECT) - a sub-90 nm space and hole patterning technology using 248-nm lithography and plasma-enhanced polymerization

    Page(s): 562 - 564
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    A plasma polymerization coating process named Dielectric Resolution Enhancement Coating Technology (DiRECT) is proposed to shrink critical dimensions (CDs) of space and hole patterns. Fluorocarbon plasmas are used as the precursors to coat a polymer layer on the patterned photo-resist. By adding only one processing step, we are able to shrink poly space and contact hole to sub-90 nm-level using 248-nm lithography. The results of our extensive tests have demonstrated the production-worthiness of this technique for its consistent lot-to-lot repeatability, tight within-wafer CD uniformity, and low defect level. View full abstract»

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  • The hetero-epitaxial SiCN/Si MSM photodetector for high-temperature deep-UV detecting applications

    Page(s): 565 - 567
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (231 KB) |  | HTML iconHTML  

    A visible-blind ultraviolet (UV) photodetector (PD) with metal-semiconductor-metal (MSM) structure has been developed on a cubic-crystalline SiCN film. The cubic-crystalline SiCN film was deposited on Si substrate with rapid thermal chemical vapor deposition (RTCVD). The optoelectron performances of the SiCN-MSM PD have been examined by the measurement of photo and dark currents and the currents' ratio under various operating temperatures. The current ratio for 254-nm UV light of the detector is about 6.5 at room temperature and 2.3 at 200/spl deg/C, respectively. The results are better than the counterpart /spl beta/-SiC of 5.4 at room temperature, and less than 2 for above 100/spl deg/C, thus offering potential applications for low-cost and high-temperature UV detection. View full abstract»

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  • Band offset induced threshold variation in strained-Si nMOSFETs

    Page(s): 568 - 570
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (207 KB) |  | HTML iconHTML  

    Due to the offset in the valence band, strained-Si nMOSFETs exhibit a -100 mV threshold shift and 4% degradation of the subthreshold slope per each 10% increase of Ge content in the relaxed SiGe layer. The correlation between the threshold shift and strained layer thickness is investigated based on device simulations. In a certain range of the strained-Si layer thickness, the threshold and subthreshold slope change gradually, posing a concern of larger device parameter variation. A larger threshold distribution is observed in devices fabricated with a strained layer thickness comparable to the depletion depth. View full abstract»

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  • Gate field emission induced breakdown in power SiC MESFETs

    Page(s): 571 - 573
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (351 KB) |  | HTML iconHTML  

    The breakdown mechanism of SiC MESFETs has been analyzed by careful investigation of gate leakage current characteristics. It is proposed that gate current-induced avalanche breakdown, rather than drain avalanche breakdown, is the dominant failure mechanism for SiC MESFETs: thermionic-field emission and field emission are dominant for the ON state (above pinch-off voltage) and the OFF state (below pinch-off voltage), respectively. The effect of Si/sub 3/N/sub 4/ passivation on breakdown voltage has been also investigated. Si/sub 3/N/sub 4/ passivation decreases the breakdown voltage due to higher electric field at the gate edge compared to edge fields before passivation. A reduction in surface trapping effects after passivation results in the higher electric field because the depletion region formed by trapped electrons is reduced significantly. View full abstract»

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  • Characterization of low-temperature processed single-crystalline silicon thin-film transistor on glass

    Page(s): 574 - 576
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (242 KB) |  | HTML iconHTML  

    Single-crystalline silicon thin film on glass (cSOG) has been prepared using an "ion-cutting" based "layer-transfer" technique. Low-temperature processed thin-film transistors, fabricated both on cSOG and metal-induced laterally crystallized polycrystalline silicon, have been characterized and compared. The cSOG-based transistors performed comparatively better, exhibiting a significantly higher electron field-effect mobility (/spl sim/430 cm/sup 2//Vs), a steeper subthreshold slope and a lower leakage current that was also relatively insensitive to gate bias. View full abstract»

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  • Hydrogenated amorphous silicon thin-film transistor arrays fabricated by digital lithography

    Page(s): 577 - 579
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1000 KB) |  | HTML iconHTML  

    A jet-printed digital-lithographic method, in place of conventional photolithography, was used to fabricate 64 × 64 pixel (300 μm pitch) matrix addressing thin-film transistor (TFT) arrays. The average hydrogenated amorphous silicon TFT device within an array had a threshold voltage of /spl sim/3.5 V, carrier mobility of 0.7 cm2/V/spl middot/s, subthreshold slope of 0.76 V/decade, and an on/off ratio of 10/sup 8/. View full abstract»

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  • A high-performance multichannel dual-gate poly-Si TFT fabricated by excimer laser irradiation on a floating a-Si thin film

    Page(s): 580 - 582
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (586 KB) |  | HTML iconHTML  

    A new excimer laser annealing (ELA) process that uses a floating amorphous-Silicon (a-Si) thin film with a multichannel structure is proposed for high-performance poly-Si thin-film transistors (TFTs). The proposed ELA method produces two-dimensional (2-D) grain growth, which can result in a high-quality grain structure. The dual-gate structure was employed to eliminate the grain boundaries perpendicular to the current flow in the channel. A multichannel structure was adapted in order to arrange the grain boundary to be parallel to the current flow. The proposed poly-Si TFT exhibits high-performance electrical characteristics, which are a high mobility of 504 cm/sup 2//Vsec and a low subthreshold slope of 0.337 V/dec. View full abstract»

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  • A new a-Si:H thin-film transistor pixel circuit for active-matrix organic light-emitting diodes

    Page(s): 583 - 585
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB) |  | HTML iconHTML  

    We propose a new pixel circuit using hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs), composed of three switching and one driving TFT, for active-matrix organic light-emitting diodes (AMOLEDs) with a voltage source method. The circuit simulation results based on the measured threshold voltage shift of a-Si:H TFTs by gate-bias stress indicate that this circuit compensates for the threshold voltage shifts over 10000 h of operation. View full abstract»

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  • Polycrystalline silicon thin-film transistors fabricated by rapid Joule heating method

    Page(s): 586 - 588
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB) |  | HTML iconHTML  

    We report n- and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated with a rapid joule heating method. Crystallization of 50-nm-thick silicon films and activation of phosphorus and boron atoms were successfully achieved by rapid heat diffusion via 300-nm-thick SiO/sub 2/ intermediate layers from joule heating induced by electrical current flowing in chromium strips. The effective carrier mobility and the threshold voltage were 570 cm/sup 2//Vs and 1.8 V for n-channel TFTs, and 270 cm/sup 2//Vs and -2.8 V for p-channel TFTs, respectively. View full abstract»

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  • Three-transistor one-time programmable (OTP) ROM cell array using standard CMOS gate oxide antifuse

    Page(s): 589 - 591
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (670 KB) |  | HTML iconHTML  

    A three-transistor (3-T) cell CMOS one-time programmable (OTP) ROM array using CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high-voltage blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option of high-density CMOS OTP ROM array for modern digital as well as analog circuits. View full abstract»

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  • Improved independent gate N-type FinFET fabrication and characterization

    Page(s): 592 - 594
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (301 KB) |  | HTML iconHTML  

    N-type independent gate FinFETs (IGFinFETs) have been fabricated and characterized. Previous published results for this structure highlighted processing deficiencies. Several process enhancements have improved device results beyond those previously reported. These process improvements are presented, and the resulting device is demonstrated. Device results for 2 micron channel length devices are shown. Six decades of drain current suppression and low gate leakage currents are achieved. Subthreshold slope of 200 mV/dec and a threshold voltage tuning range of 1.7 V are demonstrated. This device combines the behavioral characteristics of independent-double-gate MOSFETs with the processing advantages and integration of FinFETs. View full abstract»

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  • Low-leakage diode string designs using triple-well technologies for RF-ESD applications

    Page(s): 595 - 597
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (250 KB) |  | HTML iconHTML  

    This letter proposes a novel low-leakage diode string designs using triple-well technologies in 0.18-μm CMOS process for RF-electrostatic discharge (RF-ESD) applications. Based on the characteristics of the low-leakage current and low-capacitance in the triple-well diode string, it is convenient to apply it in RF-ESD (electrostatic discharge) protection circuit designs. As compared to the conventional p/sup +//n-well diode string, the substrate leakage current can be kept very small all the time before the triple-well diode string turns on. It results from the existence of the parasitic base-emitter tied p-n-p bipolar transistor in each triple-well diode. View full abstract»

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  • A reassessment of ac hot-carrier degradation in deep-submicrometer LDD N-MOSFET

    Page(s): 598 - 600
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (302 KB) |  | HTML iconHTML  

    In deep submicrometer N-MOSFET, a "backdrop" of substantial defect generation by the quasi-static V/sub g/=V/sub d/ stress phase is shown to significantly influence the accuracy of interpretation of ac stress data. If neglected, a severe overestimation of ac stress induced degradation would result. Through an approach that eliminates this damage component from the overall ac stress damage, increased parametric shifts, associated with the gate pulse transition phase, are found to occur in different time windows, delineated by the relative importance of hot-hole and hot-electron induced damage at different stages of the stress, the interaction between the two damages at specific stages of the stress, as well as the sensitivities of the device parameters to the spatial evolution of the two damages. View full abstract»

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  • High-isolation bonding pad design for silicon RFIC up to 20 GHz

    Page(s): 601 - 603
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (743 KB) |  | HTML iconHTML  

    A simple depletion-insulation (DI) bonding pad structure is presented for silicon radio frequency integrated circuits (RFIC). Experimental results show that DI bonding pads can achieve a 3 to 7 dB improvement in cross-talk isolation compared with an ordinary bonding pad at all measured frequencies. An improvement of up to 90% in the Q-factor is also achieved by the DI pad indicating a significantly reduced high-frequency substrate loss. When compared with a ground-shield (GS) bonding pad, the isolation and the Q-factor of the DI bonding pad is inferior. However, the DI pad has a 40% smaller pad capacitance compared with the GS pad. The DI structure can be used in interconnect optimization to achieve high cross-talk isolation and low substrate loss, with minimal increase in parasitic capacitance. View full abstract»

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