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IEEE Network

Issue 4 • July-Aug. 2003

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Displaying Results 1 - 21 of 21
  • Practical storage area net working [Book Review}

    Publication Year: 2003, Page(s): 4
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  • Photonic slot routing in optical transport networks [Book Review]

    Publication Year: 2003, Page(s): 4
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  • System-level power optimiza tion for wireless multimedia communications [Book Review]

    Publication Year: 2003, Page(s):4 - 5
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  • Broadband applications: and the digital home [Book Review]

    Publication Year: 2003, Page(s): 5
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  • Honeypots, tracking hackers [Book Reviews]

    Publication Year: 2003, Page(s): 5
    Cited by:  Papers (1)
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  • Web hocking attacks and defense [Book Reviews]

    Publication Year: 2003, Page(s):5 - 6
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  • Practical TCP/IP designing, using and troubleshooting TCP/IP networks on linux and windows [Book Reviews]

    Publication Year: 2003, Page(s): 6
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  • Network processor design, issues and practices: volume I [Book Reviews]

    Publication Year: 2003, Page(s): 6
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  • Wireless security and privacy, best practices and design techniques [Book Reviews]

    Publication Year: 2003, Page(s):6 - 7
    Cited by:  Papers (1)
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  • Internetworking and computing over satellite networks [Book Reviews]

    Publication Year: 2003, Page(s): 7
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  • NCTUns 1. 0 [Book Review]

    Publication Year: 2003, Page(s): 9
    Cited by:  Papers (1)
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  • Visualizotion toot for ad hoc networks [Book Review]

    Publication Year: 2003, Page(s): 9
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  • SIP express router (SER) [Book Review]

    Publication Year: 2003, Page(s): 9
    Cited by:  Papers (2)
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  • Network processors [Guest editorial]

    Publication Year: 2003, Page(s):10 - 11
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  • Search engine implications for network processor efficiency

    Publication Year: 2003, Page(s):12 - 20
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (767 KB) | HTML iconHTML

    Network processors are programmable devices with special architectural features that are optimized to perform packet forwarding decisions. Those decisions are often based on data accessed from various table structures. Access to these structures typically requires one of several search methods, each of which consists of multiple individual memory accesses, leading to significant latency to complet... View full abstract»

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  • Support for software performance tuning on network processors

    Publication Year: 2003, Page(s):40 - 45
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB) | HTML iconHTML

    In response to the continuous growth in network bandwidth and application requirements, specialized chips called network processors have been built to deliver high performance and flexibility at moderate cost. Network processors often employ parallelism to achieve this high performance/cost ratio. However, the same parallelism can also make the behavior of the software difficult to understand. Whe... View full abstract»

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  • Platform level support for high throughput edge applications: the Twin Cities prototype

    Publication Year: 2003, Page(s):22 - 27
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (639 KB) | HTML iconHTML

    Even in the face of increasing network bandwidth, there is a desire among service providers to improve network security, availability, and performance. These improvements require increasingly complex computations on network packets. Current networking platforms cannot keep up, leading to less than desired throughput or functionality. Network processors deliver high networking throughput, but not t... View full abstract»

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  • Creating advanced functions on network processors: experience and perspectives

    Publication Year: 2003, Page(s):46 - 54
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (755 KB) | HTML iconHTML

    In this article we present five case studies of advanced networking functions that detail how a network processor (NP) can provide high performance and also the necessary flexibility compared with ASIC. We first review the basic NP system architectures, and describe the IBM PowerNP architecture from the data plane as well as the control plane point of view. We introduce models for the programmer's... View full abstract»

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  • DiffServ edge routers over network processors: implementation and evaluation

    Publication Year: 2003, Page(s):28 - 34
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB) | HTML iconHTML

    Network processors are emerging as a programmable alternative to the traditional ASIC-based solutions in scaling up the data plane processing of network services. This work, rather than proposing new algorithms, illustrates the process of, and examines the performance issues in, prototyping a DiffServ edge router with IXP1200. The external benchmarks reveal that although the system can scale to a ... View full abstract»

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  • Design and performance of a network-processor-based intelligent DSLAM

    Publication Year: 2003, Page(s):56 - 62
    Cited by:  Papers (3)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (583 KB) | HTML iconHTML

    We present the architecture, design, and evaluation of a software-centric intelligent DSLAM (digital subscriber line access multiplexer) prototype made up of an IXP network-processor-based data plane and an IXC control-processor-based control plane. This work demonstrates that versatile and programmable network nodes can be built using network processors without undermining system performance. The... View full abstract»

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  • Network processors applied to IPv4/IPv6 transition

    Publication Year: 2003, Page(s):35 - 39
    Cited by:  Papers (6)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (491 KB) | HTML iconHTML

    We describe a high-speed IPv6-IPv4 gateway on an experimental board containing a pair of Intel IXP network processor chips, an FPGA, and a pair of TCAMs. The device is capable of supporting several hundreds of thousands of concurrent TCP/UDP sessions and sustaining close to the line rate on a GbE link. It provides an order of magnitude improvement in packet throughput over an implementation of the... View full abstract»

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Aims & Scope

As currently defined, IEEE Network covers the following areas: 1. network protocols and architectures, 2. Protocol design and validation, 3. Communication software and its development and test, 4. Network control and signalling, 5. network management, 6. Practical network implementations including local area networks, (LANs), metropolitan area networks (MANs), and wide  area networks, (WANs), 7. Switching and processing in integrated (voice/data) networks and network components, 8. Micro-to-host communication.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Nei Kato
Tohoku University, Japan
kato@it.is.tohoku.ac.jp