By Topic

Electron Device Letters, IEEE

Issue 7 • Date July 2003

Filter Results

Displaying Results 1 - 24 of 24
  • Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

    Page(s): 421 - 423
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB)  

    The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thermal modeling and measurement of GaN-based HFET devices

    Page(s): 424 - 426
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (354 KB) |  | HTML iconHTML  

    In this letter, we present our thermal study results of GaN-based heterojunction field effect transistors (HFETs). In thermal computation, PAMICE code was used to calculate temperatures in a three-dimension (3-D) model. In the thermal measurement, nematic liquid crystal thermography was employed to determine the peak temperature on the surface of the device chip. The calculated and directly measured temperatures agree well. These methods are valuable in predicting the thermal performance of GaN-based HFET devices, in particular the power devices. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-power high-speed operation of submicron InP-InGaAs SHBTs at 1 mA

    Page(s): 427 - 429
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (521 KB) |  | HTML iconHTML  

    Scaling of submicron InP-InGaAs HBTs is investigated for low-power high-speed applications in mixed signal circuits. Device performance for transistors fabricated with a 0.5-μm emitter width and varying emitter lengths are studied. The 0.5 μm×2 μm devices yielded excellent low-current RF performance, with an fT=173 GHz and an fmax=187 GHz at 1 mA, the highest values reported for InP-based devices to date. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Measurement of base and collector transit times in thin-base InGaAs/InP HBT

    Page(s): 430 - 432
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (250 KB) |  | HTML iconHTML  

    The influence of base thickness reduction on performances of heterojunction bipolar transistors (HBTs) is examined. HBT structures are grown, with a base thickness in the range 25-65 nm and doping concentration from 3/spl times/10/sup 19/ to 6/spl times/10/sup 19/ at/cm/sup 3/. Base transit time is accurately extracted from total base-collector transit time, and described using a simple drift-diffusion approach. This model, however basic, shows very good agreement with measurements when usual parameter values are used. A 0.13-ps transit time reduction is measured when thinning the base from 65 to 25 nm. The thinnest base structure presents a 0.08 ps transit time, allowing a 250 GHz f/sub t/ operation at 270 kA/cm/sup 2/ emitter current density. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wideband DHBTs using a graded carbon-doped InGaAs base

    Page(s): 433 - 435
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (265 KB) |  | HTML iconHTML  

    We report an InP/InGaAs/InP double heterojunction bipolar transistor (DHBT), fabricated using a mesa structure, exhibiting 282 GHz f/sub /spl tau// and 400 GHz fmax. The DHBT employs a 30 nm InGaAs base with carbon doping graded from 8/spl middot/10/sup 19//cm3 to 5/spl middot/10/sup 19//cm3, an InP collector, and an InGaAs/InAlAs base-collector superlattice grade, with a total 217 nm collector depletion layer thickness. The low base sheet (580 /spl Omega/) and contact (<10 /spl Omega/-μm2) resistivities are in part responsible for the high fmax observed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Vertical scaling of 0.25-μm emitter InP/InGaAs single heterojunction bipolar transistors with fT of 452 GHz

    Page(s): 436 - 438
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    Vertical scaling of the epitaxial structure has allowed submicron InP/InGaAs-based single heterojunction bipolar transistors (SHBTs) to achieve record high-frequency performance. The 0.25×16 μm2 transistors, featuring a 25-nm base and a 100-nm collector, display current gain cut-off frequencies fT of 452 GHz. The devices operate at current densities above 1000 kA/cm2 and have BV/sub CEO/ breakdowns of 2.1 V. A detailed analysis of device radio frequency (RF) parameters, and delay components with respect to scaling of the collector thickness is presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of the composition on the electrical properties of TaSi/sub x/Ny metal gate electrodes

    Page(s): 439 - 441
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (293 KB) |  | HTML iconHTML  

    In this letter, the effect of silicon and nitrogen on the electrical properties of TaSi/sub x/N/sub y/ gate electrode were investigated. The TaSi/sub x/N/sub y/ films were deposited on SiO/sub 2/ using reactive cosputtering of Ta and Si target in Ar and N/sub 2/ ambient. The thermal stability of TaSi/sub x/N/sub y//SiO/sub 2//p-type Si stacks was evaluated by measuring the flatband voltage and equivalent oxide thickness at 400/spl deg/C and 900/spl deg/C in Ar. It was found that under high temperature anneals, Si-rich TaSi/sub x/N/sub y/ films increased and this was attributed to the formation of a reaction layer at the electrode-dielectric interface. Reducing the Si content alone did not prevent the formation of this reaction layer while removing Si completely by utilizing TaN resulted in work functions that were too high. The presence of both Si and N was deemed necessary and their content was critical in obtaining optimized TaSi/sub x/N/sub y/ gates that are suitable for NMOS devices. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Lanthanide (Tb)-doped HfO2 for high-density MIM capacitors

    Page(s): 442 - 444
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (230 KB) |  | HTML iconHTML  

    A high-density metal-insulator-metal (MIM) capacitor with a lanthanide-doped HfO2 dielectric prepared by physical vapor deposition (PVD) is presented for the first time. A significant improvement was shown in both the voltage coefficient of capacitance (VCC) and the leakage current density of MIM capacitor, yet the high capacitance density of HfO2 dielectrics was maintained by achieving the doping of Tb with an optimum concentration in HfO2. This technique allows utilizing thinner dielectric film in MIM capacitors and achieving a capacitance density as high as 13.3 fF/μm2 with leakage current and VCC values that fully meet requirements from year 2005 for radio frequency (RF) bypass capacitors applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Observation of nitrogen-enhanced doping deactivation at the polysilicon-oxynitride interface of pMOSFETs with 12-/spl Aring/ gate dielectrics

    Page(s): 445 - 447
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB) |  | HTML iconHTML  

    This letter reports the observation of a process integration issue that arises when large doses of nitrogen (>1/spl times/10/sup 15/ cm/sup -2/) are incorporated in oxynitride gate dielectric films targeting equivalent oxide thickness of 11-13 /spl Aring/. It is shown that capacitance-extracted active doping density at the polysilicon/oxynitride (poly/SiON) interface of boron-doped p/sup +/-polysilicon gated pMOSFETs decreases with increasing nitrogen dose of the oxynitride film as measured by X-ray photoelectron spectroscopy. A physical mechanism is proposed to explain experimental observations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Passivation of interface-states in large-area Si devices using hydrogen implantation

    Page(s): 448 - 450
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB) |  | HTML iconHTML  

    We have found that in the large-scale transistor structures, where gate oxide thickness of 6 nm and below is used, the standard post-metallization (forming gas) annealing leaves a large number of Si/SiO2 interface states unpassivated, with a lower limit of N/sub it/=5e11 cm/sup -2/. This may be due to the limited range of hydrogen (H) diffusion through the thin gate oxide and its ensuing inability to reach beyond the edges of the devices with a channel length larger than 3.0 μm. We have shown that hydrogen ion implantation can successfully remove the residual interface state by placing the hydrogen uniformly throughout the area of a large device. Remarkable improvements in all the device characteristics, including capacitance and current versus voltage and the transistor threshold behavior as a function of the channel length, was achieved by hydrogen implantation and anneal as a final processing step. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Amorphous silicon TFT-based active-matrix organic polymer LEDs

    Page(s): 451 - 453
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (925 KB) |  | HTML iconHTML  

    We report active-matrix organic polymer light-emitting displays (LEDs) based on a three hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) pixel electrode circuit that supplies a continuous output current to organic polymer light-emitting devices. The output current level drift induced by either process variations or device aging can be reduced in this design by adjusting the driver TFT operating point with the active resistor. Our first green light-emitting engineering prototype had a brightness of 120 cd/m/sup 2/ and fill factor of about 45%. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of substrate biasing on Si/SiGe heterostructure MOSFETs for low-power circuit applications

    Page(s): 454 - 456
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB) |  | HTML iconHTML  

    We have investigated the effect of substrate biasing on the subthreshold characteristics and noise levels of Si/Si/sub 1-x/Ge/sub x/ (x=0,0.15,0.3) heterostructure MOSFETs. A detailed analysis of the dependence of threshold voltage, off-state current, and low-frequency noise level on the substrate-source (V/sub bs/) biasing showed that SiGe heterostructure MOSFETs offer a significant speed advantage, an extended subthreshold operation region, a reduced noise level, and reduced bulk potential sensitivity compared to Si bulk devices. These experimental results demonstrate that SiGe heterostructure MOSFETs render a promising extension to the CMOS technologies at the low-power limit of operation, eventually making the micropower implementation of radio frequency (RF) functions feasible. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Investigation of grain boundary control in the drain junction on laser-crystalized poly-Si thin film transistors

    Page(s): 457 - 459
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB) |  | HTML iconHTML  

    This letter investigates the influences of grain boundaries in the drain junction on the performance and reliability of laser-crystalized poly-Si thin film transistors (TFTs). A unique test structure where the channel region includes 150-nm-thick laser-crystalized poly-Si with small grain sizes and a 100-nm-thick one with large grain sizes is fabricated. Different behaviors in the electrical characteristics and reliability of a single TFT are observed, first under measurements of the forward mode and then under measurements of the reverse mode. This is due to the different number of grain boundaries in the drain junction. Grain boundaries in the drain junction were found to cause reduced ON/OFF current ratio, variations in threshold voltage with drain bias, significantly increased kink effect in the output characteristics, and poor hot-carrier stress endurance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Implementation of both high-hole and electron mobility in strained Si/strained Si1-yGey on relaxed Si1-xGex (x

    Page(s): 460 - 462
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (303 KB) |  | HTML iconHTML  

    High-hole and electron mobility in complementary channels in strained silicon (Si) on top of strained Si/sub 0.4/Ge/sub 0.6/, both grown on a relaxed Si/sub 0.7/Ge/sub 0.3/ virtual substrate is shown for the first time. The buried Si/sub 0.4/Ge/sub 0.6/ serves as a high-mobility p-channel, and the strained-Si cap serves as a high-mobility n-channel. The effective mobility, measured in devices with a 20-μm gate length and 3.8-nm gate oxide, shows about 2.2/spl sim/2.5 and 2.0 times enhancement in hole and electron mobility, respectively, across a wide vertical field range. In addition, it is found that as the Si cap thickness decreased, PMOS transistors exhibited increased mobility especially at medium- and high-hole density in this heterostructure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 4H-SiC normally-off vertical junction field-effect transistor with high current density

    Page(s): 463 - 465
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (543 KB) |  | HTML iconHTML  

    4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-μm vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm2 at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm2 gives the V/sub bl/2/R/sub on-sp/ value of 830 MW/cm2, surpassing the past records of both unipolar and bipolar 4H-SiC power switches. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • N-channel MOSFETs fabricated on homoepitaxy-grown 3C-SiC films

    Page(s): 466 - 468
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    We present results of the enhancement mode, n-channel 3C-silicon carbide (SiC) MOSFETs fabricated on homoepitaxy 3C-SiC films. The fabricated devices exhibit excellent gate-controlled linear and saturation regimes of operation. The average effective channel mobility is found to be 229 cm/sup 2//Vs. The breakdown field of the gate oxide is observed at be 11 MV/cm and the subthreshold swing is determined to be 280 mV/decade. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

    Page(s): 469 - 471
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics

    Page(s): 472 - 474
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (222 KB) |  | HTML iconHTML  

    P/sup +/-poly-Si gate MOS transistors with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics (EOT=2.50 nm) have been fabricated. Similar to the reference samples with SiO/sub 2/ gate dielectrics (T/sub ox/=2.45 nm), clear saturation characteristics of drain current are obtained for the samples with stack gate dielectrics. Identical hole-effective mobility is obtained for the samples with the SiO/sub 2/ and the stack gate dielectrics. The maximum value of hole-effective mobility is the same (54 cm/sup 2//Vs) both for the stack and the SiO/sub 2/ samples. Hot carrier-induced mobility degradation in transistors with the stack gate dielectrics was found to be identical to that in transistors with the SiO/sub 2/ gate dielectrics. In addition to the suppression of boron penetration, better TDDB characteristics, and soft breakdown free phenomena for the stack dielectrics (reported previously), the almost equal effective mobility (with respect to that of SiO/sub 2/ dielectrics) has ensured the proposed stack gate dielectrics to be very promising for sub-100-nm technology generations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Direct tunneling RAM (DT-RAM) for high-density memory applications

    Page(s): 475 - 477
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (634 KB) |  | HTML iconHTML  

    A new approach to reducing the tunnel oxide thickness in floating gate memories is introduced for RAM applications. Experimental measurements and two-dimensional (2-D) device simulations are used to investigate the operating principles of a direct tunneling RAM (DT-RAM) cell. DT-RAM targets memory applications in which manufacturability, scalability, low-power, high-density, and long retention times are important considerations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Methods for noise isolation in RFCMOS ICs

    Page(s): 478 - 480
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (610 KB) |  | HTML iconHTML  

    Different process techniques of suppressing the transmission of high-frequency noise induced by fast-switching MOS gates through silicon (Si) substrate have been examined. The isolated n/sup +/-pocket structure formed by a new process technique designed in this work has proven to be most effective in guarding vulnerable devices from remnant high-frequency noise roaming in the substrate among the structures we have used in the experiment: p/sup +/ guard ring, proton implant, and pocket structures. The noise suppressing efficiency is -75 dB at 1 GHz of n/sup +/-pocket structure in contrast to -38 dB at 1 GHz of unprotected devices. The protecting structures should become a decisive measure for future success of Si-based radio frequency integrated circuit (RFIC) applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiple-terminal gate charging effect - competing/compensating charging behavior

    Page(s): 481 - 483
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (218 KB) |  | HTML iconHTML  

    The charging effect from the antenna at the multiple nodes of MOSFET devices was investigated using bulk-CMOS technology. We demonstrated experimentally that the antenna size at source and drain terminals can modulate gate charging behavior, just like that at the gate terminal. However, gate charging damage is lessened when the source and/or drain antenna size increases, which is an effect opposite to that of the gate antenna. The effect can be explained by a multiple-terminal gate charging model, revealing the competing and compensating nature of the incoming charging current among the gate, source, and drain terminal of the MOSFET. The model also indicates a similar effect for the N-well antenna in P MOSFETs. The finding here leads to an application that actually utilizes metal antennae to protect gate oxide in realistic circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching

    Page(s): 484 - 486
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (373 KB)  

    Ultranarrow and ideal rectangular cross section silicon(Si)-Fin channel double-gate MOSFETs (FXMOSFETs) have successfully been fabricated for the first time using [110]-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. The transconductance (g/sub m/) normalized by 2×(Fin height) is found to be as high as 700 μS/μm at V/sub d/=1 V in the fabricated 13-nm-thick and 82-nm-high Si- Fin channel double-gate MOSFET with a 105-nm gate length and a 2.2-nm gate oxide. The almost-ideal S-slope of 64 mV/decade is demonstrated in a 145-nm gate length device. These excellent results show that the Si-Fin channel with smooth [111]-oriented sidewalls is suitable to realize a high-performance FXMOSFET. The short-channel effects (SCEs) are effectively suppressed by reducing the Si-Fin thickness to 23 nm or less. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hot-carrier stress effects on gate-induced-drain leakage current in n-channel MOSFETs studied by hydrogen/deuterium isotope effect

    Page(s): 487 - 489
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (266 KB) |  | HTML iconHTML  

    The degradation of gate-induced-drain leakage (GIDL) current under hot-carrier stress (HCS) has been studied in n-channel MOSFETs that were annealed in hydrogen (H) or deuterium (D). It is found that the degradation of GIDL current (I/sub GIDL/) can be effectively suppressed by deuterium passivation of interface traps. By using the H/D isotope effect, the impacts of oxide charge trapping (/spl Delta/N/sub ox/) and interface trap generation (/spl Delta/N/sub it/) on I/sub GIDL/ are successfully separated. The results indicate that, depending on stress and measurement conditions, I/sub GIDL/ may increase or decrease under HCS. /spl Delta/N/sub ox/ alters I/sub GIDL/ at high electric fields by varying the band-to-band tunneling current. /spl Delta/N/sub it/ alters I/sub GIDL/ at a low electric field by introducing a trap-assisted leakage component. Furthermore, evidence of hole trapping at the peak substrate current stress is indisputably presented for the first time and its impact on I/sub GIDL/ is discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New nonvolatile memory with charge-trapping sidewall

    Page(s): 490 - 492
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    This letter reports on the development of a new nonvolatile memory with charge-trapping sidewalls using sub-0.1-μm MOSFET technology. This memory has silicon nitride (SiN) sidewalls at both sides of the gate to store the charge. We have found that optimization of the p-n junction edge with the sidewall enables writing, reading, and erasing a 2-bit charge independently. The Vth window, which is the difference in the threshold voltage between forward and reverse read, was about 0.8 V with a gate length of 0.4 μm. In addition, it is scalable to 40 nm of the gate length. This device is attractive not only from the prospects of future size reduction, but also its compatibility with CMOS process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Amitava Chatterjee